coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2024-08-26	nb/intel/haswell: Move SPD addresses to devicetree	Keith Hui
	Introduce a sandybridge-style devicetree setting for SPD addresses, and use it instead of runtime code in mb_get_spd_map() for all haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all boards except google/slippy. Patch also covers recently added Z97 boards using Broadwell MRC. Also update util/autoport to match. abuild passes for all affected boards. autoport builds, but otherwise untested. Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-06	mb/asrock: Add Z87E-ITX (Haswell)	Nicholas Chin
	This was done using Haswell autoport, with manual fixes to get the output to build against current main. I do not physically have this board; I was sent the output of autoport with some fixes on top of which I added additional changes. The VBT was copied from /sys/kernel/debug/dri/0/i915_vbt on version 2.70 of the vendor firmware. The flash chip is 8MiB in a socketed DIP8 package, making it easy to externally flash to recover from a brick. Working: - Haswell MRC.bin - S3 suspend and resume - Libgfxinit - HDMI - DVI-I (including passive DVI to VGA adapter) - DisplayPort - SATA ports - mSATA SSD - mPCIe WiFi slot - Rear USB ports - USB 3.0 header - Audio header - Ethernet - x16 PCIe slot - EHCI debug with the CH347 (top USB 2.0 port by the PS/2 connector) - edk2 (MrChromebox uefipayload_202309) Not Tested: - PS/2 keyboard/mouse - eSATA - USB 2.0 header Change-Id: I56c22d8f5505f9a4da25f8b4406b00978af1a586 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81022 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>