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2020-08-24mb/asrock: Drop unneeded empty linesElyes HAOUAS
Change-Id: I4385fded02e43f3fd8683dd926d81a59c04d3bd9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-15mainboard: Drop optional and empty ACPI \_BFS methodsAngel Pons
The ACPI specification, version 2.0 says: _BFS is an optional control method. So, remove them. They have been copy-pasted around quite a bit, and do not do anything useful. Plus, it's deprecated in later ACPI versions. Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10AMD mainboards: Drop commented-out includeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I6f71419ea23b973b0bedb426e20cb3dc460ef68d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43271 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10mb/asrock/imb-a180: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I00b3af64b6f842d298e91c20ab5f54f0ca3197ee Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09ACPI: Drop commented-out DSDT DefinitionBlock instancesAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I9b5589d4596eead83a5897b083ccb85ef05a03d5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43270 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS
Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'. Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-01src: Fix up #-commented SPDX headersAngel Pons
Delete leading empty comment lines. Change-Id: I8e14a0ad1e1e2227e4fb201f5d157f56f289f286 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-01AGESA f14/f15tn/f16kb: Clean up buildOpts.c filesAngel Pons
Until now, the buildOpts.c files were primarily made out of copy-pasted AGESA options, commented-out definitions and several useless comments; that is, the materialization of technical debt in GCC-parsable form... Until now. It is assumed that the boards in the tree still boot. So, by comparing their settings, we can extract saner defaults to place into AGESA. Many of the settings were common across all boards of the same family, so we promote those values to default settings. In some cases flipping a flag was required, so the macros to alter that option had to be adapted as well. Since those AGESA versions are expected to never receive updates, it should not be a problem to change their files to suit our needs. As a result, all but two buildOpts.c files now have less than 100 lines. AGESA f14 boards need less than 50 lines, and f15tn/f16kb just require about 60 or 70 lines in those files. Hopefully, this will make porting more mainboards using AGESA f14/f15tn/f16kb a substantially easier task. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ife1ca5177d85441b9a7b24d64d7fcbabde6e0409 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-29AGESA boards: Fix typo in *OVERRIDES* in commentPaul Menzel
Run the command below to fix all occurrences. git grep -l OVERIDES | xargs sed -i 's/OVERIDES/OVERRIDES/g' Change-Id: I5ca237500a0ecff59203480ecc3c992991f08130 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-05-26AGESA f14/f15tn/f16kb: Deduplicate RAM settingsAngel Pons
On AGESA f14/f15tn, various RAM-related options were defined in an enum. However, the preprocessor mess can't compare enum values. To make AGESA build, each board redefined them as macros, shadowing the enum elements. Clean this up by replacing the enums with macros in AGESA headers, and delete the now-redundant redefinitions from all the mainboards. Note that AGESA f16kb already uses macros, but each mainboard still had commented-out definitions. Remove them as well, as they are unnecessary. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ie1085539013d3ae0363b1596fa48555300e45172 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41666 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26AGESA f16kb: Factor out default MTRR settingsAngel Pons
All AGESA f16kb boards use the same MTRR values. Factor them out, while still allowing a board to override them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I236e9d45505e92027acc3ba5ff496f5e2f09b9f3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-26AGESA f14/f15tn/f16kb: Factor out memory settingsAngel Pons
We use the same values everywhere, so we might as well factor them out. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ie6f166034d5d642dff37730a8d83264fb2e019b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2020-05-26AGESA f14/f15tn/f16kb: Factor out PCI MMIO base/sizeAngel Pons
We set BLDCFG_PCI_MMIO_BASE and BLDCFG_PCI_MMIO_SIZE to the same values everywhere, so we might as well factor them out. As we have equivalent Kconfig options in coreboot, also deprecate overriding them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I7244c39d2c2aa02a3a9092ddae98e4ac9da89107 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-26AGESA f14/f15tn/f16kb: Factor out AGESA_VERSION_STRINGAngel Pons
We use the same AGESA version numbers on all but one mainboard, so we might as well factor them out. The only exception is asrock/e350m1, which has the f15tn/f16kb version number even though it actually uses AGESA f14. To preserve reproducibility, do not change it in this commit. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I0dad2352ccda454d5545f17228d52e4ff4f23f20 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41591 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26AGESA f14/f15tn/f16kb: Factor out AGESA_PACKAGE_STRINGAngel Pons
We use the same value everywhere, so factor it out. Note that the field where this value ends up in was doubled in size for AGESA fam16kb, but we did not update the definition to fill in the additional space. We are not changing it in this commit so as to preserve binary reproducibility. In any case, add a FIXME explaining why this value may not be correct. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ied118d534ee1e9728db843944d1e042760b4f32c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2020-05-26mb/*/*/buildOpts.c: Clean up whitespaceAngel Pons
Drop multiple blank lines and use one space inside C-style comments. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ibe1f279dd22ae7657ea7b7766f88004dbf4dceb5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2020-05-26mb/*/*/buildOpts.c: Drop BLDCFG_IR_PIN_CONTROLAngel Pons
This does not exist anywhere in the entire coreboot tree. Drop it. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I80320a20f4b44896e72d701a1d98786cb3a93dcc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2020-05-18mainboard/*/*/*.cb: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: Ia0dbf7b946d42bda11b904a9caff5a402b553b33 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-18mainboard/*/*/Kconfig*: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I7089b29e881d74d31477e2df1c5fa043fe353343 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41358 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-04mainboard/asrock: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I32c5f5e865b5455ddb7034612ecea1383932cef9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-03-25acpi: correct the processor devices scopeMichał Żygowski
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here. Additionally add processor scope patching for P-State SSDT created by AGESA, becasue AGESA creates the tables with processors in \_PR scope. TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are no errors, decompile ACPI tables with acpica to check whether the processor scope is correct and if IASL does not complain on wrong checksum, run FWTS Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18mainboard/[a-f]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-03-07mb: Use 'print("%s...", __func__)'Elyes HAOUAS
Change-Id: I4fa89dc1ad4196a61bb0cdfaa0d59dfe4c6fff12 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39231 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-13mb/asrock/imb-a180: Fix typoElyes HAOUAS
Change-Id: Iff032a321301772789a42f29cfc187c446b4cfa1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-12mb/*/*: use ACPIMMIO common block wherever possibleMichał Żygowski
TEST=boot PC Engines apu2 and launch Debian Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-09src/mainboard: remove MMIO macrosIdwer Vollering
This touches several mainboards. Replace the macro with C functions. The presence of bootblock.c is assumed. Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-20src/mainboard: Remove unused '#include <device/pci.h>'Elyes HAOUAS
Change-Id: I5791fddec8b2387df5979adbb1a0fa64c5dd23ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-20mainboard: Add missing include <device/pci_def.h>Elyes HAOUAS
Change-Id: I8a7c989540e8b62de7fd291f695adac849f4680c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-12-19mb/{asrock,asus}: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I14d3579f232b1dcc95b4e0653520686965dbe727 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-12AGESA, binaryPI: Remove generic device for SPD eepromsKyösti Mälkki
These entries have no functional purpose, followup work will disallow chip entries that do not link in the respective driver. Change-Id: Ieab695022d0dd2f2671f9058db97bdd6fb29a10d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-12asrock/imb-a180: Switch away from ROMCC_BOOTBLOCKKyösti Mälkki
Change-Id: I603e6c83d72cf6c1d8f8c6eef652fdf954a3a284 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37453 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09AGESA,binaryPI: Move PORT80 selection to C bootblockKyösti Mälkki
Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day. This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK. Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-03AGESA boards: Drop commented out codeKyösti Mälkki
Change-Id: I9db1147c5e112e5e6832eeece2214fece8aa6b83 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-30AGESA,binaryPI: Flag boards with ROMCC_BOOTBLOCKKyösti Mälkki
Allows boards to be transformed to C env bootblock one at a time. Change-Id: I1cc1910a8bfb6b3495593979cbf7194b0d82c8e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37345 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-27src/mainboard: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I46d131f76ec930d2ef0f74e6eaabae067df10754 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-19src: Drop unused 'include <cbfs.h>'Elyes HAOUAS
Change-Id: If5c5ebacd103d7e1f09585cc4c52753b11ce84d0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-12src: Drop unused 'include <arch/acpigen.h>'Elyes HAOUAS
Use <arch/acpi.h> when appropriate. Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-08commonlib/loglevel.h: Drop unnecessary includeElyes HAOUAS
This 'include' is only needed in console/console.h file. Change-Id: Ief61106eb78d0de743c920f358937c51658c228a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-06src: Drop unused include <arch/acpi.h>Elyes HAOUAS
Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-07src: Remove unused include device/pnp_def.hElyes HAOUAS
Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-16AGESA fam16kb boards: Clean up devicetreeKyösti Mälkki
Remove double nesting of chip northbridge/amd. There is requirement to keep SPD address map in the same chip block with device 0:18.2. Change-Id: Id3a161c54341d0c5c569ea6118ee6f890b7f62e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30735 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14AGESA: Remove ACPI for IMC we don't runKyösti Mälkki
IMC is used on some of the AMD reference designs, so do not touch them yet. Change-Id: Iae21e0294f0155f07fb4f4348ebc5b3120d50fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/18536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-28arch/x86: Drop spurious arch/stages.h includesKyösti Mälkki
Change-Id: I3b9217a7d9a6d98a9c5e8b69fe64c260b537bb64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19mainboard: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: I4ee3cc42302c44dc80ae1f285579a4d1775aec16 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-28mb/*/*/Kconfig: Remove useless commentElyes HAOUAS
Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hellsenberg <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2018-11-16src/mainboard: Remove unused "HW_MEM_HOLE_SIZE_AUTO_INC"Elyes HAOUAS
Change-Id: I10e89de270a20dbd28647e8b0f8a2425c515b350 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-05mainboard: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29285 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05amd: Fix non-local header treated as localElyes HAOUAS
Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29103 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02src/mb: Fix non-local header treated as localElyes HAOUAS
Also remove some unnedded includes. Change-Id: I036208a111d009620d8354fa9c97688eb4e872ad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/asrock: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ie1e319375ab0f5565805557b15e0bf821dfb223e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09mb/asrock: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I4b2b8593c98791dac7a5c016e75d2c05bcfbf890 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-01-26mb/*/*/cmos.layout: Fix the values for the console levelArthur Heymans
Fix the values that were off by one. This was discovered when using postcar stage that prints with debuglevel BIOS_NEVER. Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-05AGESA: Re-enable HAVE_ACPI_RESUMEKyösti Mälkki
Note: For some of the boards affected ACPI S3 support was never tested but feature was just copy-paste from reference design. Change-Id: I2a54d605fa267a7501f57efd79a16b3bfa49891e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2017-09-29AGESA binaryPI: Drop amdlib.h in BiosCallouts.cKyösti Mälkki
Some fam14 boards will need more work on this area, those are to be addressed with followup patches. Change-Id: I14208cf8519a4cf71e4944d08a2dae36b7f1f878 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-26AGESA: Remove heap allocations from OemCustomize.cKyösti Mälkki
We can simply declare these structures const. Change-Id: I637c60cc2f83e682bd5e415b674f6e27c705ac91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26AGESA binaryPI boards: Fix some whitespaceKyösti Mälkki
Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-19AGESA binaryPI: Clean up amdfamXX.h includeKyösti Mälkki
Change-Id: Iba8b8d33e1f10e28745234988d97d4fafd04c798 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-13AGESA vendorcode: Move PlatformInstall.hKyösti Mälkki
All thse Option.*Install.h files are about configuring what eventually is referenced in the final libagesa build. It's self-contained so isolate these together with PlatformInstall.h to hide them from rest of the build. Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA boards: Clean up Ids.h and Filecode.h includesKyösti Mälkki
Change-Id: I9cb63ff58900a39d7cd8e3da2b9a9a95c2a41a69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA boards: Drop heapManager.h includesKyösti Mälkki
Change-Id: I1a96b1c6181cd657d7aee82370ef86acd688cc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA boards: Clean up some includesKyösti Mälkki
Change-Id: I84c70aa04ab556a3898d3525f7b9aab85812f61d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25asrock/imb-a180: Remove commented oem_fan_control()Kyösti Mälkki
Change-Id: Ibfbb2ff2d9776fe91a8a09561d9c32eb49a56db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-24AGESA mainboards: Clean up IS_ENABLED fan controlMarshall Dawson
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around the imc.h includes. Convert all #if to if() for fan control setup. Change-Id: I04a9fbbf6f64f45e1a0b544267bfe840ce7fa1d9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-24asrock/imb-a180: Switch away from AGESA_LEGACY_WRAPPERKyösti Mälkki
Change-Id: I5e6e4cabe2b93c41da19412ec3ae2dfaa114bcc0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-23AGESA binaryPI: Consolidate and fix sleep statesKyösti Mälkki
SSFG was meant to be used as a mask to enable sleep states _S1 thru _S4. However as a logical instead of bitwise 'and' operation was used, all the states were enabled if only one was marked available. State _S3 is now set conditionally if HAVE_ACPI_RESUME=y. For pi/hudson this had been fixed already preprocessor. Note that all boards had SSFG == 0x0D that previously enabled ACPI S3 sleep state even when it was not available. States _S1 and _S2 still appear enabled in ASL/AML but may not actually work. TEST: 'cat /sys/power/state' and notice choice 'mem' was removed from the list of available sleep states. Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-02AGESA: Introduce AGESA_LEGACY_WRAPPER and its counterpartKyösti Mälkki
We define AGESA_LEGACY_WRAPPER a method of calling AGESA via functions in agesawrapper.c file. The approach implemented there makes it very inconvenient to do board-specific customisation or present common platform-specific features. Seems like it also causes assertion errors on AGESA side. The flag is applied here to all boards and then individually removed one at a time, as things get tested. New method is not to call AGESA internal functions directly, but via the dispatcher. AGESA call parameters are routed to hooks in both platform and board -directories, to allow for easy capture or modification as needed. For each AGESA dispatcher call made, eventlog entries are replayed to the console log. Also relocations of AGESA heap that took place are recorded. New method is expected to be compatible with binaryPI. Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-29asrock/imb-a180: Switch away from AGESA_LEGACYKyösti Mälkki
Change-Id: I00bd4d895b2585235bf5b3edd23fbcddba69d31e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18714 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28AGESA: Introduce AGESA_LEGACY and its counterpartKyösti Mälkki
We define AGESA_LEGACY as an implementation of mainboard that has its romstage main completely under mainboard/ directory. We have learnt from other platforms this approach has several downsides when it comes to making platform-wide improvements. We start by creating per-family romstage.c file, which boards will gradually take into use by removing the AGESA_LEGACY Kconfig option we here apply to all of them. Change-Id: Id01931e185a023039a60af16a678de9966db8d65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18619 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07AGESA: Add agesa_helper.h headerKyösti Mälkki
These definitions do not require AGESA.h include, and we will eventually remove agesawrapper.h files. Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-07AGESA: Remove leftover s3resume includeKyösti Mälkki
Change-Id: I7a1574259f73a52b66d03c686ae8ab70345c36ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18586 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-07AGESA: Remove leftover agesawrapper includeKyösti Mälkki
Change-Id: Ib37989ee7535e59b1903537995f8383d8b04387c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18584 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-26amd-based mainboards: Fix whitespace in _PTS commentsMarshall Dawson
Correct tabs that were intended as spaces. Change-Id: Idcf33d829f87a866b5ed880527102918d5b93842 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17905 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-12-22agesa and binaryPI mainboards: Fix devicetree hudson commentsMarshall Dawson
Make the ending comment associated with "chip ...hudson" match the appropriate directory name. Change-Id: I5e0d6d41a2e3f963760aad08ed6108acac5b66b3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17904 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-12-06cpu/amd/mtrr.h: Drop excessive includesKyösti Mälkki
Change-Id: Id404bdab1f2361f1e7d20f7ee72111971863dddf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17736 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/x86/msr.h: Drop excessive includesKyösti Mälkki
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05mainboard & southbridge: Clear files that are just headersMartin Roth
These headers & comments indicating a lack of functionality don't help anything. We discourage copyrights and licenses on empty files, so just clear these. Change-Id: Id2ab060a2726cac6ab047d49a6e6b153f52ffe6d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17657 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-01AGESA: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-07src/mainboard: Remove whitespace after sizeofElyes HAOUAS
Change-Id: Ie2a047d35e69182812c349daedc5b3b5fde20122 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16860 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-26mainboard/*/*/mptable.c: Improve code formattingElyes HAOUAS
Change-Id: I341293cd334d6d465636db7e81400230d61bc693 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16723 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31mainboard: Format irq_tables.cPaul Menzel
Run the command below to format the files `irq_tables.c` of (mostly AMD) mainboards correctly with GNU indent 2.2.10. ``` $ git grep -l 'if (sum != pirq->checksum) {' | xargs indent -l ``` Fix up the following two checkpatch.pl errors manually. ``` ERROR: that open brace { should be on the previous line #1219: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:129: + uint8_t reg[8] = + { 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63 }; ERROR: that open brace { should be on the previous line #1221: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:131: + uint8_t irq[8] = + { 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07 }; ``` This is needed, so that follow-up commits, fixing checkpatch.pl errors and warnings, won’t run into conflicts with the git commit hooks, when for example, spaces instead of tabs are used for indentation. Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/15932 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-04AGESA boards: Split dispatcher to romstage and ramstageKyösti Mälkki
The way dispatcher table is set up prevents linker from optimizing unused code away, we currently have raminit in ramstage. Optimize this manually by configuring AGESA_ENTRY booleans for romstage and ramstage separately. This will remove references in FuncParamsInfo and DispatchTable -arrays. All boards now include multi-core dispatcher, it has minimal footprint: AGESA_ENTRY_LATE_RUN_AP_TASK ACPI S3 support depends on HAVE_ACPI_RESUME being enabled: AGESA_ENTRY_INIT_RESUME AGESA_ENTRY_INIT_LATE_RESTORE AGESA_ENTRY_INIT_S3SAVE Disabled for all boards as it was not used: AGESA_ENTRY_INIT_GENERAL_SERVICES Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14417 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03AMD boards: Drop comment on include fileKyösti Mälkki
The included file does not declare pm_ioread(), and the modified file does not call it either. Change-Id: I9723caf1062db23b4a3648e07c2dc4c02f862619 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14968 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03AGESA boards: Drop unused includeKyösti Mälkki
These files do not use definitions from OptionsIds.h. Also those definitions are required and already included for Ids.h. Change-Id: I149fcfe2ad72fe3d7390ee2043a86432aeae3f08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14980 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10AGESA boards: Relocate platform memory configKyösti Mälkki
File buildOpts.c is a can of worms, pull platform memory configuration in to OemCustomize.c. This array should be assigned at runtime instead of linking a modified defaults table. Change-Id: I73d9d3fbc165e6c10472e105576d7c40820eaa6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14528 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10AGESA boards: Rename files containing OEM configurationKyösti Mälkki
There are other things besides PCIe port configuration that require board specific hooks. Change-Id: I0923651487b9ed5f6f7569ce08e02d993fa5f976 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12AMD/Kabini: Fix the interrupt routingZheng Bao
The plugged devices on PCIe should use IOAPIC2 instead of standard IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1. The unchanged code worked because the OS uses MSI instead APIC. To test that, boot linux with parameter pci=nomsi and see if the devices like NIC work well as they do without the booting parameter. run 'cat /proc/interrupts' to see if the devices actually use no-msi. Change-Id: Id6d35224312aeb6e3a175ec9990e0bb34bad67e7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12362 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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