| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-11-25 | cpu/intel/haswell: Move chip_ops to cpu cluster | Arthur Heymans |
| 2022-11-09 | nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetree | Arthur Heymans |
| 2021-01-15 | cpu/intel/haswell: Factor out ACPI C-state values | Angel Pons |
| 2020-11-10 | sb/intel/lynxpoint/sata: Always use AHCI mode | Angel Pons |
| 2020-07-28 | lynxpoint: Factor out PIRQ routing from devicetree | Angel Pons |
| 2020-07-26 | mb/*/*/devicetree.cb: Normalize disabled PIRQ values | Angel Pons |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-05-10 | src/mainboard: Replace GPLv2 long form headers with SPDX header | Elyes HAOUAS |
| 2020-03-18 | mainboard/[a-f]*: Remove copyright notices | Patrick Georgi |
| 2018-12-28 | sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports | Tristan Corrick |
| 2018-11-16 | mainboard: Add ASRock H81M-HDS | Tristan Corrick |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |