coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-12-05	nb/intel/x4x: Remove apic 0 from devicetree	Arthur Heymans
2022-12-05	cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm	Arthur Heymans
2022-12-02	sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}	Elyes Haouas
2022-12-01	nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree	Arthur Heymans
2021-10-05	src/mainboard to src/security: Fix spelling errors	Martin Roth
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-10	src/mainboard: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS
2020-03-18	mainboard/[a-f]*: Remove copyright notices	Patrick Georgi
2019-11-12	sb/intel/i82801gx: Add common LPC decode code	Arthur Heymans
2019-06-06	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans
2019-06-05	mb/*/devicetree.cb: Remove unavailable PCIe ports	Arthur Heymans
2018-11-12	mb//: Harmonise FD and devicetree on boards featuring ICH7	Arthur Heymans
2018-09-15	mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree	Arthur Heymans
2018-07-22	mb/asrock/g41c-gs: Add the revision 1 variant	Arthur Heymans