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2022-11-15soc/amd: commonize generation of the PIC/APIC mapping tablesFelix Held
Now that we have a common init_tables in all mainboards using AMD SoCs, both the population of the fch_pic_routing and fch_apic_routing arrays and the definition of those arrays can be moved to the common AMD SoC code to not have the code duplicated in all mainboards. BUG=b:182782749 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26mb/amd/bilby,birman,chausie,majolica: rework FCH IRQ mapping generationFelix Held
This ports the changes to the way the fch_pic_routing and fch_apic_routing arrays get populated from Mandolin to Bilby, Birman, Chausie and Majolica. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia957056b60dafbc52a9809a4563a348ad7443376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd,google: unify fch_irq_routing struct instance nameFelix Held
Use the same fch_irq_map name in all mainboards using the Picasso, Cezanne, Mendocino and Morgana instead of using a mainboard-specific name. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I035cffb9c6c8afd6bd115831e8eed4a395e2a7fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIESFelix Held
Instead of using magic constants for the fch_pic_routing and fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the common code headers and use this definition. This also allows to drop the static assert for the array sizes. In the Stoneyridge mainboard code the equivalent arrays are named mainboard_picr_data and mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array size there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26mb/amd,google: move fch_irq_routing struct definition to soc/amdFelix Held
Define the fch_irq_routing struct once in a common header file instead of in every mainboard's code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I11d9000b6ed7529e4afd7f6e8a7332c390da6dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/68817 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24mb/amd/chausie,majolica: don't select HAVE_ACPI_RESUMEFelix Held
The Chausie and Majolica boards use S0ix which is mutually exclusive with S3, so don't select HAVE_ACPI_RESUME. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d1bf33ad017dfbf908e0a195949998668c8e137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64605 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12soc/amd/*/Makefile.inc: Do some cosmeticsArthur Heymans
The first target for the add_intermediate targets is always $(obj)/coreboot.pre. Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-04-07ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-01mb/amd/majolica/port_descriptors: clean up variable namesFred Reitberger
Removing unnecessary "czn" in variable name. Majolica is always a cezanne. TEST=Timeless build Change-Id: I490111ecea84c934585d0bbd623486fba76eb7f1 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63261 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23soc/amd/cezanne: Turn off gpp clock request for disabled devicesRobert Zieba
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled, checked that physically removing a device that is marked as enabled also disables the corresponding clk req BRANCH=guybrush Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-12mb/amd/majolica/mainboard: add initial IRQ routingFelix Held
This IRQ routing info is taken from mb/google/guybrush. The IRQ routing on Chausie that was a 1:1 copy caused some issues with the I2C driver, so port the Chausie IRQ mapping change back to Majolica. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb958639dd8aef7c60c050ad107dde7d1cd6a8bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03soc/amd/*/i2c: factor out common I2C pad configurationFelix Held
The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-31mb/amd/majolica: Add variant to disable HDMIZheng Bao
For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. Please refer src/mainboard/google/guybrush/variants/dewatt/variant.c Change-Id: I8d7637467d2f16377d3c3064cdb0934d1658fdf7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/mainboard/amd: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ie06cfa598f40a734994abb2bc2eb8f01f9331f7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11ChromeOS: Replace with or add <types.h>Kyösti Mälkki
It's commented in <types.h> that it shall provide <commonlib/helpers.h>. Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of other includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05mb/google,intel: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23soc/amd: rename program_gpios to gpio_configure_padsFelix Held
Use the same function name as in soc/intel for this functionality. This also brings the function name more in line with the extended version of this function gpio_configure_pads_with_override which additionally supports passing a GPIO override configuration. This might cause some pain for out-of-tree boards, but at some point this should be made more consistent, so I don't see a too strong reason not to do this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-08-28mb/(amd,google): Update SPI Kconfig settings based on devicetreeMartin Roth
This takes the devicetree SPI settings and moves them into Kconfig. BUG=b:195943311 TEST=boot guybrush & majolica and verify spi settings. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-27mb/amd/majolica/Kconfig: add EFS SPI settingsFelix Held
This keeps the default of EFS_SPI_SPEED at 66.66Mhz for the non-EM100 case, but switches the EFS_SPI_READ_MODE setting from Dual IO (1-1-2) to Quad IO (1-1-4) for the non-EM100 case. This patch adds a special config for the EM100 emulator case that has limited SPI frequency support. Tested on Majolica by Martin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8996c2bf606ccd21686092beac8d96b22c0b7869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56815 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05mb/amd/majolica:Enable IOMMU Device for majolicaJason Glenesk
Enable IOMMU PCIe device. BUG=b:194173037 TEST=lspci shows IOMMU device 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631 Cq-Depend: chrome-internal:4027293,4027294 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: Ia84276ca98163158d818a0efc3e021b93ab365de Reviewed-on: https://review.coreboot.org/c/coreboot/+/56771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-26mb/*: Specify type of `FMDFILE` onceAngel Pons
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07soc/amd/cezanne: Configure I2C Pad RX Select through devicetreeKarthikeyan Ramasubramanian
Some of the I2C buses are required to operate at different voltage level compared to other I2C buses eg. I2C bus to Google Security Chip (GSC) should be at 1.8V level. By default, all the I2C buses are initialized to operate at 3.3 V. Add support to configure I2C pad RX select through devicetree and update the concerned devicetree. BUG=b:188538373 TEST=Build and boot to OS in Guybrush. Ensure that the communication with GSC is fine. Build Majolica mainboard. Change-Id: I595a64736fdac0274abffb68c5e521302275b845 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-27mb/amd/majolica: enable crypto coprocessor PCIe deviceFelix Held
This fixes the following error from the Linux kernel: ccp 0000:03:00.2: ioremap failed ccp 0000:03:00.2: initialization failed ccp: probe of 0000:03:00.2 failed with error -12 BUG=b:186575712,b:189202985 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id1c6a6cbbdda2cb22e81e2b52b364617d6765e09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54963 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27mb/amd/majolica: set PSPP policy to balancedFelix Held
BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5fd0021170777c755ecb78d339aec05ff786710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54932 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14mb/amd/majolica: Disable IO ports 0x60/0x64Raul E Rangel
I suspect there is additional initialization required to enable the 8042 keyboard controller on the EC. By removing the range we no longer encounter long 20 second delays when reading the IO ports. Since depthcharge polls the IO ports it makes it seem like depthcharge locked up. BUG=b:182100027 TEST=Boot majolica with depthcharge to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I56a7eb4200e4615e1b4d9f14594d64f93e031a54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06soc/amd/common/espi,mb/: Allow configuring open drain ALERT#Raul E Rangel
Some designs might wish to use an open drain eSPI ALERT#. This change adds an enum that allows setting the eSPI alert mode. BUG=b:187122344, b:186135022 TEST=Boot guybrush using all 3 alert modes Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06mb/amd/majolica: Enable S0i3 by defaultJason Glenesk
Set s0ix_enable to true. BUG=b:178728116 TEST=Cold boot and perform a cycle of S0i3. Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-28mb/amd/majolica:Set IRQ for GPIO controllerJason Glenesk
AMD GPIO driver will not load if IRQ is not set. As a consequence, it does not clear the interrupt when waking from S0i3. BUG=178728116 TEST=Perform 2 S0i3 cycles, confirming second cycle does not return instantly due to first interrupt not being cleared. Change-Id: I3072263e8e68f939a47ed4125444c60133087824 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-19mb/amd/majolica: use GPIO_40 as reset pin for NVME SSDNikolai Vyssotski
Default Majolica configuration uses GPIO_40 for NVME M2_SSD_RST# BUG=b:182100027 TEST=ls /dev/nvme* Change-Id: Idecc0ec7eaf903b29fea109d3688f3c249da62f5 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-16soc/amd/cezanne: Add uart controllers to chipset.cbIvy Jian
Add uart controller to chipset.cb and leave it off by default. Turn uart0 on for console for mainboards. BUG=none TEST=builds and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-12mb/amd/majolica/port_descriptor: use GPIO number defineFelix Held
TEST=Timeless build results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie39dc99bef4eb3776388d7406239bac6031bfaaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/52193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/amd/majolica: add DXIO and DDI descriptorsFelix Held
TEST=Worked on Matt's Majolica board. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Change-Id: I65c7e0ebf1e43fd4608d46bae8a176cfc3d0236b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51956 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07mb/amd/majolica: add PCIe devices to devicetreeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I838aeda2e6c403eaa3388a6b934e7ab6b4e918e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSPMatt Papageorge
This patch adds the functionality to write the DXIO and DDI descriptors to the UPD data structure to the SoC code and adds the mainboard_get_dxio_ddi_descriptors function to each mainboard using the Cezanne SoC that gets called to get the descriptors from the board code. Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-29mb/amd: majolica,mandolin: Remove needless article from warningPaul Menzel
At the end of the built, the line below is printed. coreboot has been built without an the Microchip EC FW. Remove *an*, as one article is enough. Change-Id: I28b24f0f2dade17e30e16cc6d935976e331a7a97 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-25mb/amd/majolica: Enable IO port 2E/2FZheng Bao
MEC1701 can be accessed by IO port 2E/2F Change-Id: I31f1b147476ec487e64f3c30b3cf514b45ced416 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-22mb/amd/majolica: Set IOMUX to enable I2C2 & I2C3Zheng Bao
Change-Id: I142c06c150214d58acc04b8c6b3b027fff0256db Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-03-18mb/amd/majolica: Generate OIPG PackageRaul E Rangel
This fixes the unknown reference errors for OIPG. Since Majolica doesn't actually have any of the GPIOs ChromeOS uses, we leave the arrays empty. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifeae84e0ccab187a4e7131cd6ea9e1336d79df67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51536 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/amd/majolica,google/guybrush,google/mancomb: select HAVE_ACPI_RESUMERaul E Rangel
Since not all mainboards based on the Cezanne SoC have to support ACPI resume, select this option in the mainboard's Kconfig and not in the SoC's Kconfig. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I988276ccb5b61837d7f3f015d1d1aba783324b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11mb/amd/majolica: Enable USB ACPI in devicetreeMathew King
BUG=b:180529005 TEST=boot majolica, all USB ports work Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I6d3506bb4d54c7f8ea1e53576ef68d2aface6c89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10mb/amd/majolica: Update to use proper APCBs built for MajolicaMatt Papageorge
Some of the previous binaries were incorrect and should not be used for Majolica because they are templates instead of APCBs specifically built for the board. This APCB update also places the UMA region under 4G and size 32 MB which is essential for video output. TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory region size, base and alignment. Change-Id: Id797e2ad5bd67815c09752aedc19dad7dcf8ad12 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-03mb/amd/majolica: Add eSPI supportZheng Bao
Change-Id: I3e82a51173f561df560c36528a9b7ec26cf489b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-02mb/amd/majolica: Enable required devices in devicetreeMathew King
Most devices are now disabled by default in the chipset. Enable the iGPU and two XHCI controllers that are required to boot the board. BUG=b:180528708 TEST=To be tested Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I54a4547217fb8e9f67fc0c8e1e36e96dfaae331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51095 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01mb/: Drop print of MAINBOARD_PART_NUMBERKyösti Mälkki
Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-24mb/amd,google: Rename static functions to mainboard_enableKyösti Mälkki
Let's not have 7 boards of all use a different name for the .enable_dev function in mainboard chip_operations. Change-Id: I07f3569e6af85f4f1635595125fe2881ab9ddd43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-24mb/amd,google/zork: Move init_tables() callKyösti Mälkki
The semantics of pirq_setup() from previous platforms was to only setup the global pointers for PIC and APIC tables, not to create or modify the tables themselves. Change-Id: Iaa7c31eed21432dc2b3fe6b32803bd2658fd5e2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14soc/amd/cezanne: move CPU cluster to chipset device treeFelix Held
This will be common for all boards, so move it to the chipset device tree. TEST=CPU cluster and LAPIC still show up in console logs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia49e7b4cfc09c60b6152b8ccc47f37b6adc1e319 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50613 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14mb/amd/majolica/mainboard: Set ACPI IRQRaul E Rangel
We now pass the ACPI SCI IRQ to the OS, so make sure the board routes it correctly. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1b4d5e0bfb1d9df9ac8a8c41cdf466a67f2673d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-02-13mb/amd/majolica: Add plain dsdtRaul E Rangel
Needed to enable ACPI support for cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifd71635d3493e0cf104b60ecf94ebdf70d512b94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12mb/amd/majolica/devicetree: add CPU clusterFelix Held
Change-Id: I8d8b7f3ea2502e4e49a1290b07d84d5bbb2924a7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50506 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12mb/amd/majolica: Add FCH IRQ routingRaul E Rangel
I left most everything as NC since we don't expose the values to the OS yet. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7c3195ef27091f1bc61892c475ffe09137b63083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50511 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11mb/amd/majolica: Add chromeos supportRaul E Rangel
This change enables vboot support. To use it add CHROMEOS=y to your config. TEST=Boot majolica and see verstage run, and then see depthcharge load. coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 verstage starting (log level: 8)... Phase 1 FMAP: area GBB found @ 805000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 Phase 2 Phase 3 FMAP: area GBB found @ 805000 (458752 bytes) FMAP: area VBLOCK_A found @ 30000 (8192 bytes) FMAP: area VBLOCK_A found @ 30000 (8192 bytes) VB2:vb2_verify_keyblock() Checking keyblock signature... VB2:vb2_verify_digest() HW RSA forbidden, using SW VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW FMAP: area VBLOCK_A found @ 30000 (8192 bytes) FMAP: area VBLOCK_A found @ 30000 (8192 bytes) VB2:vb2_verify_fw_preamble() Verifying preamble. VB2:vb2_verify_digest() HW RSA forbidden, using SW VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW Phase 4 FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes) VB2:vb2api_init_hash() HW crypto forbidden by TPM flag, using SW VB2:vb2_verify_digest() HW RSA forbidden, using SW VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW Saving secdata firmware Saving secdata kernel Saving nvdata Slot A is selected FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes) CBFS: mcache @0x02017000 built for 9 files, used 0x1ec of 0x800 bytes CBFS: Found 'fallback/romstage' @0x0 size 0x753c in mcache @0x02017000 BS: verstage times (exec / console): total (unknown) / 116 ms coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 romstage starting (log level: 8)... Family_Model: 00a50f00 FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes) CBFS: Found 'fspm.bin' @0x15440 size 0x2257d in mcache @0x02017138 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-04mb/amd/majolica: add fmd for use when building chromeosMathew King
BUG=b:177909472 TEST=builds Change-Id: I5eb3c60fe60e4029485fae642c88c5c013ffb3f6 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50208 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30mb/amd/majolica: Add an empty bootblock function to handle GPIOZheng Bao
Change-Id: I35da3812a424ea1beef86d043a756a87e6afdaa3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50117 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30mb/amd/majolica: Add an empty function of mainboard bootblockZheng Bao
Change-Id: I985405b51c81d1e5a3a593bfb759e9850beb2244 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-22mb/amd/majolica: Add PSP support for board majolicaZheng Bao
Change-Id: Ia2470a7297c7003c7975c7d9b977f2f97174efea Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48529 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18mb/amd/majolica: Add option of ROM sizeZheng Bao
Change-Id: I07740285658aa098d3785cbead173b2f3acca42d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-15build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi
They all operate on that file, so just add it globally. Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-14build system: Structure and serialize INTERMEDIATEPatrick Georgi
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14mb/amd/majolica: use integrated UART as consoleFelix Held
Change-Id: Ic6dcbe999234f233fbac8fbdb06d22c8577b1a40 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11soc/amd/cezanne: add 0xcf9 resetFelix Held
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05mb/amd/majolica: add functionality to add EC blob to buildFelix Held
Without the EC blob being present in the SPI flash, the board won't even power up. Change-Id: Ia3c50e86414bbc707bc33e28c636196c1be2f1e6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05mb/amd/majolica: add skeleton of Cezanne reference boardFelix Held
This is an adapted copy of mainboard/example/min86 that is currently only used for Jenkins to test the SoC code in soc/amd/cezanne and isn't expected to reach boot block at the moment. It will be extended in future follow-up commits. Change-Id: I6806955952fbfa3227294cfc44fdf9156140e933 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 21:43:06 +0000