index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
gitea
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
mainboard
/
51nb
/
x210
/
devicetree.cb
Age
Commit message (
Expand
)
Author
2020-07-29
soc/intel/skylake: Enable TraceHub depending on devicetree configuration
Felix Singer
2020-07-29
soc/intel/skylake: Enable SMBus depending on devicetree configuration
Felix Singer
2020-07-29
soc/intel/skylake: Enable LAN depending on devicetree configuration
Felix Singer
2020-07-29
soc/intel/skylake: Enable SATA depending on devicetree configuration
Felix Singer
2020-07-26
skylake boards: Factor out copy-pasted PIRQ routes
Angel Pons
2020-05-18
skylake: update processor power limits configuration
Sumeet R Pawnikar
2020-05-04
soc/intel/skl: always enable SataPwrOptEnable
Michael Niewöhner
2020-04-10
src/mb: Remove unneeded spaces before/after tabs
Elyes HAOUAS
2020-03-31
mb/51nb/x210: restore left USB3 port in devicetree
Matt DeVillier
2020-03-29
mb/51nb/x210: Fix up USB ports in devicetree
Matt DeVillier
2020-03-16
mb/51nb/x210: update devicetree
Matt DeVillier
2020-03-16
mb/51nb/x210: add libgfxinit support
Matt DeVillier
2020-03-16
mb/51nb: Add support for the 51nb X210
Matthew Garrett