Age | Commit message (Expand) | Author |
2022-12-05 | cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm | Arthur Heymans |
2020-09-14 | src/include: Drop unneeded empty lines | Elyes HAOUAS |
2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
2020-04-05 | src/include: Use SPDX for GPL-2.0-only files | Angel Pons |
2020-03-17 | src (minus soc and mainboard): Remove copyright notices | Patrick Georgi |
2018-10-11 | src: Move common IA-32 MSRs to <cpu/x86/msr.h> | Elyes HAOUAS |
2018-10-05 | src: Fix MSR_PKG_CST_CONFIG_CONTROL register name | Elyes HAOUAS |
2017-12-11 | intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c | Elyes HAOUAS |
2017-11-30 | intel: Replace msr(0x198) with msr(IA32_PERF_STATUS) | Elyes HAOUAS |
2016-11-09 | cpu/intel: Add MSR to support enabling turbo frequency | Shaunak Saha |
2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
2015-02-16 | acpi: Generate valid ACPI processor objects | Timothy Pearson |
2013-05-10 | Drop prototype guarding for romcc | Stefan Reinauer |
2013-02-11 | Intel: Replace MSR 0xcd with MSR_FSB_FREQ | Patrick Georgi |
2013-02-09 | speedstep: Deduplicate some MSR identifiers | Patrick Georgi |
2012-11-05 | Overhaul speedstep code | Nico Huber |
2012-11-01 | Merge cpu/intel/acpi.h into cpu/intel/speedstep.h | Nico Huber |
2012-04-06 | Fixes and Sandybridge support for lapic cpu init | Stefan Reinauer |
2010-12-11 | factor out cpu power management base into a separate file. And fix a bug in | Stefan Reinauer |