coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2023-09-12	arch/x86: Reduce max phys address size for Intel TME capable SoCs	Jeremy Compostella
2021-06-22	soc/intel/car: Add support for bootguard CAR	Arthur Heymans
2021-06-21	soc/intel/common: Add InSMM.STS support	Angel Pons
2021-06-15	cpu/intel/msr.h: Sort MSRs in ascending order	Angel Pons
2021-06-15	cpu/intel/msr.h: Add license header	Angel Pons
2021-05-28	cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe	Arthur Heymans
2021-01-07	cpu/intel: add PC10 residency counter MSR	Michael Niewöhner
2020-10-31	cpu/intel/common: correct MSR for the Nominal Performance in CPPC	Michael Niewöhner
2020-10-24	cpu/intel/common: rework code previously moved to common cpu code	Michael Niewöhner
2020-10-24	{cpu,soc}/intel: deduplicate cpu code	Michael Niewöhner
2020-10-21	{cpu,soc}/intel: replace AES-NI locking by common implemenation call	Michael Niewöhner
2020-10-19	cpu/intel/common: rework AES-NI locking	Michael Niewöhner
2020-10-19	soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code	Michael Niewöhner