| Age | Commit message (Collapse) | Author |
|---|
|
These enums & macros will be used to report resources with acpigen_*
functions (Currently those resources are reported in northbridge.asl,
but follow-up CLs will remove this file and add the need acpigen code).
BUG=b:148759816
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage' builds correctly.
Tested on an Anahera device which successfully boots to ChromeOS
with kernel version 5.10.109-15688-g857e654d1705.
Change-Id: I5b95c9b8370db63537eb48b640ad8f0e750efd69
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65768
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The MP_IRQ flags can be used in the MP table and the ACPI MADT table.
Move them into acpi.h to avoid pulling in the full mpspec.h which is
only available on x86.
BUG=b:218874489, b:160595155
TEST=Build
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f1091b7629a6446fa399720b0270556a926401a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
This provides a way in which to describe various devices required
D-states to enter LPM (S0ix). The information can be used to help
in diagnostics and understanding of S0ix entry failure.
Values were derived from Intel document 595644 (rev 0.45) and
the ADL FSP sample ASL.
This implementation adds support for ADL. Other SoC's could be
ported to be included as well. If they aren't, they will default
to the existing behavior of a single hardcoded device to ensure
compatibility with Windows.
TEST=Built and tested on brya by verifying SSDT contents
Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
|
|
Some platforms have retimers which can be configured via the EC. Add a
handle to these retimer devices to the Type C connector device, using
devicetree references.
BUG=b:208883648
TEST=Verify disassembled SSDT on brya.
BRANCH=None
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
hardwaremain.c is the common ramstage entry to all platforms so move
out ACPI code generation (x86 specific) to boot state hooks.
Another reason to do this is the following:
On some platforms that start in dram it makes little sense to have
separate stages. To reduce the complexity we want to call the ramstage
main function instead of loading a full stage. To make this scheme
more maintainable it makes sense to move out as much functionality
from the 'main' function as possible.
Change-Id: I613b927b9a193fc076ffb1b2a40c617965ce2645
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63414
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) add
support for TBAT device under \_SB.DPTF
BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TBAT device
Device (TBAT)
{
Name (_HID, "INTC1061") // _HID: Hardware ID
Name (_UID, "TBAT") // _UID: Unique ID
Name (_STR, "Battery Participant") // _STR: Description String
Name (PTYP, 0xC)
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817)
Add support for TPWR device under \_SB.DPTF
BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TPWR device
Device (TPWR)
{
Name (_HID, "INTC1060") // _HID: Hardware ID
Name (_UID, "TPWR") // _UID: Unique ID
Name (_STR, "Power Participant") // _STR: Description String
Name (PTYP, 0x11)
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62944
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The ACPI RSDP can only be found in:
- legacy BIOS region
- via UEFI service
On some systems like ARM that legacy BIOS region is not an option, so
to avoid needing UEFI it makes sense to expose the RSDP via a coreboot
table entry.
This also adds the respective unit test.
Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62573
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ide854e5c8e2ed507548047cb6e1fad49efaffbb8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Change-Id: I8b209da90b5a591f62e760961c64c4c63e6ef65b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: I6a0e9b33c6a1045a3a4a6717487525b82d41e558
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
|
|
Support of MENU key (aka hamburger) for Chromebooks with Vivaldi
keyboard
BUG=b:215038215
TEST=manually tested on Anahera device: pressing T13 key opens menu
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I07873dd9385c743a6512408688ec44a5e97219f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61835
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ie8535d97e883d3fed9414fb5ba65a0797b989c0d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Change-Id: I2fd8470ed2b8e8f00de4ba64258aac1db52744c1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This patch adds two ACPI macros for USB port A and C _PLD object
configuration as:
1. ACPI_PLD_TYPE_A
2. ACPI_PLD_TYPE_C
The configurable parameters are
- Panel, Port is exposed on which face of a panel.
- Horizontal, Horizontal position on the panel where the device
connection point resides.
- Group
- Token, Unique numerical value identifying a group.
- Position, Identifies this device connection point’s position
in the group (i.e. 1st, 2nd).
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I245b17019b6d3c5e380c16cb3c9f4edc4dd10cc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
The patch moves the CPPC_PACKAGE_NAME macro definition from file
acpi/acpigen.c to include/acpi/acpigen.h file since the
CPPC_PACKAGE_NAME method will get called from cpu/intel/common
in a later patch.
TEST=Built the code for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ic547445cdbe2b1a3efe44390bd127f577386e7fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Some acpigen code may use mutexes, and it is a common idiom to pass
a value for the Timeout field of 0xffff, which is interpreted by OSPM
to mean "no timeout". Therefore add a macro for this value.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I16bc9f3f04dd1e3dc0f3eca3e56377e6f48132b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
These values make more sense as an enum, and are currently unused in
ASL files, therefore they can be moved to the appropriate part of the
header file and converted there.
Change-Id: I8b8586b46823b5da3614a0b2a2f2f16802e96962
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
This will allow us to preload the dsdt.aml file.
BUG=b:179699789
TEST=Build guybrush
| 80 - write tables | 1.564 | 1.08 Δ( -0.48, -0.03%) |
| 85 - finalize chips | 15.483 | 13.543 Δ( -1.94, -0.14%) |
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Some boards may use more than 4 temperature sensors for DPTF thermal
control, so this patch adds support for one more temperature sensor.
BUG=b:207585491
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibf9666bade23b9bb4f740c6c4df6ecf5227cfb45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Given EC CON and associated USB port objects, custom_pld or pld_group
information is retrieved from port and added to ACPI table as _PLD field
for typec connector.
BUG=b:202446737
TEST=emerge-brya coreboot & SSDT dump in Brya test device
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ibc56ecd4e8954ffaace3acd9528a064b5fa2cf6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Some elements in the ACPI CPPC table allow static DWORDs. Instead of
using a fake register resource, use a tagged union with the two types
"register" and "DWORD" and respective macros for CPPC table entries.
Test: dumped SSDT before and after do not differ.
Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Make the `get_cst_entries()` function provide a read-only pointer. Also,
constify the actual data where applicable.
Change-Id: Ib22b3e37b086a95af770465a45222e9b84202e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
The `acpigen_write_CST_package` and `acpigen_write_CST_package_entry`
functions don't modify the provided C-state information. So, make the
pointer parameters read-only to enforce this. Also constify arguments
where possible.
Change-Id: I9e18d82ee6c16e4435b8fad6d467e58c33194cf4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
As long as there is only one PCI segment we do not need
more complicated MCFG generation.
Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Make use of the newly introduced ACPI macros for CPPC table generation
that currently exists of a bunch of confusing assignments of structs
that only get partially filled.
Test: dumped SSDT before and after do not differ.
Change-Id: I844d191b1134b98e409240ede71e2751e51e2159
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
These will be used in the follow-up change.
Change-Id: I4723ffaf0adff8cb5b1717600ed4d1634768e2b7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add TPCH as participant for dptf control functionality.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I17c0c6cfb7804dd2caa188acc93f1a63b47cab36
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Since the value returned by _DSM function 0 for a given UUID is trivial
to calculate, add the ability to do so to the
acpigen_write_dsm() functions.
Change-Id: Id9be050442485b42202cf91649aa94e56f35032a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Also change scan code from e02b to e01e. This is trying to fill the gaps in the standard table. The advise from Googler is using e01e for the keyboard backlight toggle key.
BUG=b:194146863
BRANCH=none
TEST=check on evtest
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I402192ff354f30da35aec43202df9f1407911d34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56763
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Chromebook have some platform need support MICMUTE and KBDILLUMTOGGLE.
BUG=b:194146863
BRANCH=none
TEST=check on evtest
type 4 (EV_MSC), code 4 (MSC_SCAN), value ab
type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), 1
type 4 (EV_MSC), code 4 (MSC_SCAN), value 9b
type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 1
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: Ic39ecb3118e885c9e6d84d7b78bf435cb903d17e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
|
|
Since the specification isn't very clear on this, add a comment about
the optional raw data part of a acpi_generic_error_status block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6df7d2f216fe0515e89d08c8ed01f06d19461429
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The new function is called acpigen_write_if_cond_refof(), and it must
be paired with a following acpigen_write_if_end() call.
Change-Id: I6e192a569f550ecb77ad264275d52f219eacaca1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
After ChromeOS NVS was moved to a separate allocation and the use
of multiple OperationRegions, maintaining the fixed offsets is not
necessary.
Use actual structure size for OperationRegions, but align the
allocations to 8 bytes or sizeof(uint64_t).
Change-Id: I9c73b7c44d234af42c571b23187b924ca2c3894a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Allocate chromeos_acpi in CBMEM separately from GNVS.
Change-Id: Ide55964ed53ea1d5b3c1c4e3ebd67286b7d568e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
acpi_soc_get_bert_region only gets called when a chipset's Kconfig
selects the ACPI_BERT option in which case the chipset code needs to
implement this function. In the case of acpi_soc_get_bert_region not
being implemented, but ACPI_BERT being selected for a chipset this patch
changes the behavior from never generating a BERT ACPI table to a build
error which is more obvious and easier to catch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id479fce823d8534a7790f39125d1a2b3635fc029
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55277
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Check if the ACPI_BERT Kconfig option is selected and only then try to
generate the BERT table. Also remove the acpi_is_boot_error_src_present
weak function from the ACPI global compilation unit and use the return
value of acpi_soc_get_bert_region to determine if there is a valid BERT
region with logged errors.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2a281f5f636010ba3b2e7e097e9cf53683022aea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The return value indicates if the function has found valid BERT data and
wrote them to the region and length parameters. This will be used in a
follow-up patch to remove the acpi_is_boot_error_src_present function
call in the common code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaaa3eed51645e1b3bc904c6279d171e3a10d59be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55053
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
acpi_device_add_power_res currently generates a `_STA` method hardcoded
to ON. This change enables the ability to generate a `_STA` method that
queries the status of the GPIOs to determine if the power resource is ON
or OFF.
BUG=b:184617186
TEST=Dump SSDT table for guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I91410556db002c620fd9aaa99981457808da93a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic354824468f016a7857c6990024ae87db6fd00bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
|
|
Generic Initiator Affinity structure is introdcued in ACPI spec 6.3.
This structure is used to define NUMA affinity domain which is
established by generic initiator (such as by CXL device).
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ic6ef01c59e02f30dc290f27e741027e16f5d8359
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
|
|
Add initial HMAT (Heterogeneous Memory Attribute Table) support based
on ACPI spec 6.4 section 5.2.27.
Add functions to create HMAT table (revision 2) and create HMAT Memory
Proximity Domain Attribute (MPDA) Structure.
TESTED=Simulated HMAT table creation on OCP DeltaLake server, dumped
the HMAT table and exmained the content. HMAT table and one MPDA
structure are added.
OCP Delatake server is based on Intel CooperLake Scalable Processor
which does not support CXL (Compute Express Link). Therefore solution
level testing is not done.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
BUG=b:186166365
TEST=Compiles
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Icf88477143049119036c00276f9a01985dc0b4d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The boolean is stored in ChromeOS NVS, not GNVS.
Change-Id: I5c424a052d484228a456f8f0ad4fb0bed3165e09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Move the support code for filling ChromeOS GNVS from
acpi/chromeos-gnvs.c to vc/google/chromeos/gnvs.c.
Change-Id: I7e92206561812eb3dc69739df49b6c3a93853858
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50612
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This adds full EINJ support with trigger action tables. The actual
error injection functionality is HW specific. Therefore, HW specific
code should call acpi_create_einj with an address where action table
resides. The default params of the action table are filled out by the
common code. Control is then returned back to the caller to modify or
override default parameters. If no changes are needed, caller can
simply add the acpi table. At runtime, FW is responsible for filling
out the action table with the proper entries. The action table memory
is shared between FW and OS. This memory should be marked as reserved
in E820 table.
Tested on Deltalake mainboard. Boot to OS, load the EINJ driver (
modprobe EINJ) and verify EINJ memory entries are in /proc/iomem.
Further tested by injecting errors via the APEI file nodes. More
information on error injection can be referenced in the latest ACPI
spec.
Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rocky Phagura
|
|
This change adds the ATC_REQUIRED flag for the address translation cache
indicator and fixes the devices scope entry in the SATC reporting
structure. The SoC integrated devices in the specified PCI segment
with address translation caches are a type of PCI Endpoint Device.
BUG=None
TEST=Built image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I57b3551f11502da48f3951da59d9426df5a40723
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Low Power Idle States defines additional information not present in the
_CST.
See ACPI Specification, Version 6.3 Section 8.4.4.3 _LPI.
BUG=b:178728116, b:185787242
TEST=Boot guybrush and dump ACPI tables
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I4f5301b95ff8245facaf48e2fbd51cc82df2d8cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
See ACPI Specification, Version 6.3, Section 6.2.11 _OSC (Operating
System Capabilities)
We can add more UUIDs and capability flags in the future.
BUG=b:178728116
TEST=Builds
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6e2ac1e1b47b284489932d6ed12db9d94e8d7310
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
The SoC integrated address translation cache(SATC) reporting structure
is added to Virtualization Technology for Directed I/O specification
Rev3.2. This change adds an ACPI Name-Space Device Declaration structure
SATC which has type 5 reporting structure.
BUG=None
TEST=Built image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I91d1384083c98b75bcbdddd9cc7b7a26fab25d9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51776
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia666bd0e5db40d7873532dc22bc89be9854b903a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Until now every AML package had to be closed using acpigen_pop_len().
This commit introduces set of package closing functions corresponding
with their opening function names. For example acpigen_write_if()
opens if-statement package, acpigen_write_if_end() closes it.
Now acpigen_write_else() closes previously opened acpigen_write_if(),
so acpigen_pop_len() is not required before it.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51106
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.
Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This is a magic value that means all processors.
See Table 5-52 Local APIC NMI Structure in ACPI Spec 6.3.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic2fc060fda21bec44258bcae62ddb230be542759
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Crash Data are collected and sent to the OS via the ACPI BERT.
BUG=None
TEST=Built, and BERT successfully generated in the crashLog flow.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df
Signed-off-by: Nikunj A. Dadhania <nikunj.dadhania@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
acpigen_write_name_zero() and acpigen_write_name_one() are not
implemented correctly, and are not used anywhere. Drop them in
favor of the more flexible acpigen_write_name_integer() function.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I116fd41624a8e8b536d18d747f21d3131b734dfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.
Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
With the common <soc/nvs.h> approach platform does not
need to implement the common accessors or sizeof() function.
Change-Id: I1050a252f765c763c1ae2d1610cbfb0d973ba026
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Create uniform logging for the (unlikely) case of a CBMEM
entry disappearing.
Change-Id: I7c5414a03d869423c8ae5192a990fde5f9582f2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
We currently have a mixture of calls used to determine
global ACPI S3 state. Reduce the boilerplate, ultimately
acpi_wakeup_is_s3() should be the only to keep.
Change-Id: Iff950d2bcf7eacbbdd40865abf62c35a2e8c3c69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47694
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.
If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.
If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.
Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.
Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I61a9b07ec3fdaeef0622df82e106405f01e89a9e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48719
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I515e830808a95eee3ce72b16fd26da6ec79dac85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48718
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace acpi_create_gnvs() under soc/ to reflect their
changed functionality.
Change-Id: I61010f64a4a935f238e6dcd0f8c1340a6cc68eb4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add support for the Intel LPIT table to support reading Low Power Idle
Residency counters by the OS. On platforms supporting S0ix sleep states
there can be two types of residencies:
* CPU package PC10 residency counter (read from MSR via FFH interface)
* PCH SLP_S0 assertion residency counter (read via memory mapped
interface)
With presence of one or both of these counters in the LPIT table, Linux
dynamically adds the corresponding attributes to the cpuidle sysfs
interface, that can be used to read the residency timers:
* /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
* /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
The code in src/acpi implements generic LPIT support. Each SoC or
platform has to implement `acpi_fill_lpit` to fill the table with
platform-specific LPI state entries. This is done in this change for
soc/intel/common, while being added as its own compilation unit, so SoCs
not yet using common acpi code (like Skylake) can use it, too.
Reference:
https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf
Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1
boots without crashing with an INTERNAL_POWER_ERROR.
- Windows and Linux tested on google/akemi together with CB:49046
- Linux tested on clevo/cml-u, supermicro/x11ssmf together with CB:49046
Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Rename these to soc_fill_gnvs() and move the callsite away
from mb/.
Change-Id: I760c36f65c6122103f2be98fc11ee13832c2772e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48716
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Rename acpi_create_gnvs() functions under mb/ to reflect
their changed functionality.
Remove now empty mb/acpi_tables.c files.
Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Name the common part of GNVS initialisation as soc_fill_gnvs().
It is also moved before the call to acpi_create_gnvs(), which
followup will rename to mainbord_fill_gnvs() to reflect that
implementation is under mb/.
Change-Id: Ic4cf1548b65a86212d6e45d460fcd23bb8036365
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48706
Reviewed-by: Lance Zhao
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These boards without ChromeEC do not set ACTIVE_EC_RW
flag as part of the gnvs_assign_chromeos() function.
Create abstraction to avoid <vendorcode/chromeos/x> include.
Change-Id: Ic6029e1807fcfe7dd2c766ce8221e347b6b096f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add cb support to publish CRAT ACPI object in native coreboot.
BUG=b:155307433
BRANCH=Zork
Change-Id: I5fb7c15b11414f6d807645921c0ff1ab927e6e0f
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
We need this to happen prior to SMM module loader. If
there is some debugging output it's better they do not
appear in the middle of CPU bringup.
Change-Id: I45b4b5c0c5bf8bee258a465d1e364bfe98190e44
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I2e7f22ccccc6c0df8e7e9f354c50893a53a41714
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: I9fc2d1cdbb280f781045882bc4ac98c67946953e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
It was supposed to return true for both S2 and S3, but
level S2 was never stored in acpi_slp_type or otherwise
implemented.
Change-Id: Ida0165e647545069c0d42d38b9f45a95e78dacbe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Id4728b637c784ee2bff7b175e13f4c10419b7f1b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
acpigen_write_debug_namestr() - Debug = NAME
acpigen_write_return_namestr() - Return (NAME)
acpigen_set_package_op_element_int() - Set package pointer element
DeRefOf (PKG[ELEM]) = INT
acpigen_get_package_element() - Get package (not pointer) element
dest_op = PKG[ELEM]
acpigen_set_package_element_int() - Set package element to integer
PKG[ELEM] = INT
acpigen_set_package_element_namestr() - Set package element to namestr
PKG[ELEM] = NAME
acpigen_write_delay_until_namestr_int() - Delay while waiting for
register to equal expected value.
BUG=b:160996445
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I9b20a23872b7d4a50f03761032426ffbb722b9ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47196
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update operation region spaces according to ACPI Release 6.3 Errata A.
Change-Id: I05305c96a2170eaf651d71ac79b67653745108a2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I6abbf98398057b9774fcfd9046ba933b5286e4cd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This structure is not modified so it can be made const and allow
the calling function to also declare it as a const structure.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Id8cdfb4b3450a5ab2164ab048497324175b32269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46258
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The 'struct acpi_gpio' arguments passed to acpigen functions are
not modified so they can be made const, which allows drivers to
also use a const pointer.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I59e9c19e7bfdca275230776497767ddc7f6c52db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46257
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Provide a helper function for the ACPI shift left operator that
uses the same operator for the source and result.
ShiftLeft (OP, count, OP)
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I66ee89bd1c4be583d0e892b02535bfa9514d488a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46256
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add helpers for some store operations:
Store(INTEGER, NAME) ex: Store (100, SAVE)
Store(INTEGER, OP) ex: Store (100, Local0)
Change-Id: Ia1b3f451acbfb2fc50180a8dcd96db24d330c946
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46255
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add an option for unused/reserved bits in a Field definition,
allowing for declarations that do not start at bit 0:
Field (UART, AnyAcc, NoLock, Preserve)
{
, 7, /* RESERVED */
BITF, /* Used bit */
}
These just use byte 0 instead of a name.
Change-Id: I86b54685dbdebacb0834173857c9341ea9fa9a46
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46254
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change is required for use-cases like GPIO based I2C multiplexer
where more than one GPIOs are used as select lines.
BUG=b:169444894
TEST=Build and boot waddledee to OS. Ensure that the GPIO bindings for
an array of GPIOs are added to the ACPI table as follows:
Device (MUX0)
{
...
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
"\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x0125
}
GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
"\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x0126
}
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"mux-gpios",
Package (0x08)
{
\_SB.PCI0.I2C3.MUX0,
Zero,
Zero,
Zero,
\_SB.PCI0.I2C3.MUX0,
One,
Zero,
Zero
}
}
}
})
}
Change-Id: I7c6cc36b1bfca2d48c84f169e6b43fd4be8ba330
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: Ie044f786e5deae3a1317091de67dc03c74531bfb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This to replace DSDT revison number with macro so we can adapt all boards
at once if needed.
Change-Id: I9e92a5f408f69aa1a6801bc2cba8ddfe2180b040
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add new generic helper functions for PSS, PCT, XPSS, objects.
BUG=b:155307433
TEST=Boot Morphius and dump SSDT. Confirm PSS and PCT objects appear
as expected and conform to ACPI_6_3_May16.pdf ACPI specification.
Check XPSS against Microsoft "Extended PSS ACPI Method Specification"
XPSS_spec.doc April 2, 2007.
BRANCH=Zork
Change-Id: I1ea218bcee33093481e82390550ff96d9d2cb8b5
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add the following functions to acpi AML generation code:
acpigen_write_to_integer_from_namestring()
acpigen_write_create_byte_field()
acpigen_write_create_word_field()
acpigen_write_create_dword_field()
acpigen_write_create_qword_field()
BUG=b:163583825
Change-Id: Ida151aff68f90012b16df2383fb96ddb87c3fb9c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44641
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add code for IVRS generation to coreboot. Publish coreboot generated
structure rather than IVRS generated by FSP binary.
Reference Doc: 48882_IOMMU_3.05_PUB.pdf
BUG=b:155307433
TEST=Boot trembyle to shell and extract and compare IVRS tables and make
sure they cover the same devices.
Change-Id: I693f4399766c71c3ad53539634c65ba59afd0fe1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Remove the obscure path in source code, where ACPI S3 resume
was prohibited and acpi_resume() would return and continue
to BS_WRITE_TABLES.
The condition when ACPI S3 would be prohibited needs to be
checked early in romstage already. For the time being, there
has been little interest to have CMOS option to disable
ACPI S3 resume feature.
Change-Id: If5105912759427f94f84d46d1a3141aa75cbd6ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I746ea7805bae553a146130994d8174aa2e189610
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as
reset register in FADT. How unsurprising. We might as well use that
information to automatically fill in the FADT accordingly. So, do it.
To avoid having x86-specific code under arch-agnostic `acpi/`, create a
new optional `arch_fill_fadt` function, and override it for x86 systems.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
In the initial DPTF refactor, the scope of the TCPU device was
incorrectly set as \_SB, instead of \_SB.PCI0. However, because of the
way that the acpi_inject_dsdt() callback currently works (it injects
contents before the dsdt.aml file), the Scope where the TCPU
device lives (\_SB.PCI0) doesn't exist yet. Therefore, to avoid playing
games with *when* things are defined in the DSDT, switch to defining all
of the DPTF devices in the SSDT.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia4922b4dc6544d79d44d39e6ad18c6ab9fee0fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43529
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
ACPI names can only be 4 characters long. Define a constant that defines
the size of the name + the NUL terminator.
BUG=b:154756391
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iad230c029f324005620ddad66c433ada26be78cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43329
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
A fairly common thing in ACPI is notifying a device when some kind of
device-specific event happens; this function simplifies writing this
pattern.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0f18db9cc836ec9249604452f03ed9b4c6478827
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42102
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
\_SB.DPTF.IDSP adverties to the DPTF daemon which policies the
implementation supports. Added a new acpigen function to figure out
which policies are used, and fills out IDSP appropriately.
Change-Id: Idf67a23bf38de4481c02f98ffb27afb8ca2d1b7b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
DPTF has several options on how to control the fan (fine-grained speed
control, minimum speed change in percentage points, and whether or not
the DPTF device should notify the Fan if it detects low speed).
Individual TSRs can also set GTSH, which is the amount of hysteresis
inherent in the measurement, either from circuitry (if analog), or in
firmware (if digital).
BUG=b:143539650
TEST=compiles
Change-Id: I42d789d877da28c163e394d7de5fb1ff339264eb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
