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authorEran Mitrani <mitrani@google.com>2022-07-11 10:46:46 -0700
committerMartin L Roth <gaumless@tutanota.com>2022-07-16 23:21:03 +0000
commitf39e29624adfe867f211499db5174560c3b0d487 (patch)
treec7f8339314fdd7038ded36c98bd247804a84bf1f /src/include/acpi
parentfc9f88292dbad51fc33d2902149fb83efbba51c4 (diff)
include/acpi: Add macros & definitions for resources types and flags
These enums & macros will be used to report resources with acpigen_* functions (Currently those resources are reported in northbridge.asl, but follow-up CLs will remove this file and add the need acpigen code). BUG=b:148759816 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Change-Id: I5b95c9b8370db63537eb48b640ad8f0e750efd69 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65768 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/acpi')
-rw-r--r--src/include/acpi/acpigen.h66
1 files changed, 66 insertions, 0 deletions
diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h
index 2a3e930d4d..4af7460ccb 100644
--- a/src/include/acpi/acpigen.h
+++ b/src/include/acpi/acpigen.h
@@ -210,6 +210,72 @@ enum region_space {
REGION_SPACE_MAX,
};
+enum acpi_resource_type {
+ RSRC_TYPE_MEM = 0,
+ RSRC_TYPE_IO = 1,
+ RSRC_TYPE_BUS = 2
+};
+
+enum acpi_decode_type {
+ DECODE_10,
+ DECODE_16
+};
+
+enum acpi_read_write_type {
+ READ_ONLY,
+ READ_WRITE
+};
+
+enum acpi_cacheable_type {
+ NON_CACHEABLE,
+ CACHEABLE
+};
+
+enum acpi_resource_subtype {
+ DWORD_IO,
+ DWORD_MEMORY,
+ IO,
+ MEMORY_32_FIXED,
+ QWORD_MEMORY,
+ WORD_BUS_NUMBER
+};
+
+/* macros for ACPI Table 6.49 Memory Resource Flag (Resource Type = 0) */
+#define MEM_RSRC_FLAG_TRNSL_TYPE_STATIC 0x0
+#define MEM_RSRC_FLAG_TRNSL_TYPE_TRANSLATION (0x1 << 5)
+#define MEM_RSRC_FLAG_ADDR_RNG_MEM 0x0
+#define MEM_RSRC_FLAG_ADDR_RNG_RSV (0x1 << 3)
+#define MEM_RSRC_FLAG_ADDR_RNG_ACPI (0x2 << 3)
+#define MEM_RSRC_FLAG_ADDR_RNG_NVA (0x3 << 3)
+#define MEM_RSRC_FLAG_MEM_ATTR_NON_CACHE 0x0
+#define MEM_RSRC_FLAG_MEM_ATTR_CACHE (0x1 << 1)
+#define MEM_RSRC_FLAG_MEM_ATTR_CACHE_WRT (0x2 << 1)
+#define MEM_RSRC_FLAG_MEM_ATTR_CACHE_PREFETCH (0x3 << 1)
+#define MEM_RSRC_FLAG_MEM_READ_ONLY 0x0
+#define MEM_RSRC_FLAG_MEM_READ_WRITE 0x1
+
+/* macros for ACPI Table 6.50 I/O Resource Flag (Resource Type = 1) */
+#define IO_RSRC_FLAG_ENTIRE_RANGE 0x3
+#define IO_RSRC_FLAG_ISA_ONLY 0x2
+#define IO_RSRC_FLAG_NON_ISA_ONLY 0x1
+#define IO_RSRC_FLAG_TRASL_TYPE_STATIC 0x0
+#define IO_RSRC_FLAG_TRNSL_TYPE_TRANSLATION (0x1 << 4)
+#define IO_RSRC_FLAG_SPRS_TRASL_DENSE 0x0
+#define IO_RSRC_FLAG_SPRS_TRNSL_SPARSE (0x1 << 5)
+
+/* macro for ACPI Table 6.51 Bus Number Range Resource Flag (Resource Type = 2) */
+#define BUS_NUM_RANGE_RESOURCE_FLAG 0x0 // reserved
+
+/* General Flags for WORD Address Space Descriptor Definition (ACPI Table 6.47, byte 4)*/
+#define ADDR_SPACE_GENERAL_FLAG_MAX_FIXED (0x1 << 3)
+#define ADDR_SPACE_GENERAL_FLAG_MAX_NOT_FIXED 0x0
+#define ADDR_SPACE_GENERAL_FLAG_MIN_FIXED (0x1 << 2)
+#define ADDR_SPACE_GENERAL_FLAG_MIN_NOT_FIXED 0x0
+#define ADDR_SPACE_GENERAL_FLAG_DEC_SUB (0x1 << 1)
+#define ADDR_SPACE_GENERAL_FLAG_DEC_POS 0x0
+#define ADDR_SPACE_GENERAL_FLAG_CONSUMER 0x10
+#define ADDR_SPACE_GENERAL_FLAG_PRODUCER 0x0
+
struct opregion {
const char *name;
enum region_space regionspace;