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This commit is adding a dependency check for the FSP_USE_REPO
config option which so far was not able to deal with IceLake
systems.
Change-Id: I29faa8d3acff5680b611951fc193d33f514dc0d3
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37561
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for the FSP feature to display the logo.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Iaaffd2be567861371bbe908c1ef9d7dde483a945
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This patch removes the recently added update8/16/32/64() API and
replaces it with clrsetbits8/16/32/64(). This is more in line with the
existing endian-specific clrsetbits_le16/32/64() functions that have
been used for this task on some platforms already. Rename clrsetbits_8()
to clrsetbits8() to be in line with the new naming.
Keep this stuff in <device/mmio.h> and get rid of <mmio.h> again because
having both is confusing and we seem to have been standardizing on
<device/mmio.h> as the standard arch-independent header that all
platforms should include already.
Also sync libpayload back up with what we have in coreboot. (I'm the
original author of the clrsetbits_le32-definitions so I'm relicensing
them to BSD here.)
Change-Id: Ie4f7b9fdbdf9e8c0174427b4288f79006d56978b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37432
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adds a generic graphics driver that can be added to a devicetree which
populates graphics-related ACPI table. It will write the _DOD method
(Enumerate All Devices Attached to the Display Adapter) and a device
object for each device defined. The device may optionally have a
connected privacy screen which can be controlled with a _DSM.
Example:
chip drivers/generic/gfx
register "device_count" = "1"
register "device[0].name" = ""LCD""
register "device[0].addr" = "0x0400"
register "device[0].privacy.enabled" = "1"
register "device[0].privacy.detect_function" = ""\\_SB.PCI0.PVSC.GPVD""
register "device[0].privacy.status_function" = ""\\_SB.PCI0.PVSC.GPVX""
register "device[0].privacy.enable_function" = ""\\_SB.PCI0.PVSC.EPVX""
register "device[0].privacy.disable_function" = ""\\_SB.PCI0.PVSC.DPVX""
device generic 0 on end
end
ASL
Scope (\_SB.PCI0.GFX0)
{
Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices
{
Return (Package (0x01)
{
0x00000400
})
}
Device (LCD)
{
Name (_ADR, 0x0400) // _ADR: Address
Name (_STA, 0x0F) // _STA: Status
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
ToBuffer (Arg0, Local0)
If ((Local0 == ToUUID ("c7033113-8720-4ceb-9090-9d52b3e52d73")))
{
ToInteger (Arg2, Local1)
If ((Local1 == Zero))
{
Local2 = \_SB.PCI0.PVSC.GPVD ()
If ((Local2 == One))
{
Return (Buffer (One)
{
0x0F
})
}
}
If ((Local1 == One))
{
ToBuffer (\_SB.PCI0.PVSC.GPVX (), Local2)
Return (Local2)
}
If ((Local1 == 0x02))
{
\_SB.PCI0.PVSC.EPVX ()
}
If ((Local1 == 0x03))
{
\_SB.PCI0.PVSC.DPVX ()
}
Return (Buffer (One)
{
0x00
})
}
Return (Buffer (One)
{
0x00
})
}
}
}
BUG=b:142237145
TEST=Added gfx to devicetree on sarien_cml and correct ASL in SSDT
Change-Id: Ida520dd7aad81ee7c1e5f2d0d3f5cc1a766d78a0
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36041
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These were often used to distinguish CAR_GLOBAL variables that weren't
directly usable. Since we're getting rid of this special case, also get
rid of the marker.
This change was created using coccinelle and the following script:
@match@
type T;
identifier old =~ "^(g_.*|.*_g)$";
@@
old
@script:python global_marker@
old << match.old;
new;
@@
new = old
if old[0:2] == "g_":
new = new[2:]
if new[-2:] == "_g":
new = new[:-2]
coccinelle.new = new
@@
identifier match.old, global_marker.new;
@@
- old
+ new
@@
type T;
identifier match.old, global_marker.new;
@@
- T old;
+ T new;
@@
type T;
identifier match.old, global_marker.new;
@@
- T old
+ T new
= ...;
There were some manual fixups: Some code still uses the global/local
variable naming scheme, so keep g_* there, and some variable names
weren't completely rewritten.
Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Use proper int to pointer conversions.
Tested on Lenovo T410 with x86_64 enabled. Still works.
Change-Id: I4ed62297fb47d7d83d4b28e80f3770de99ce70f7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37393
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I81a610a6d119745f2fc637629b8ba7ade76503bc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I46e318333e68b999b2889f51fa2fbf140a27a54e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This simplifies transition and reviews towards C environment
bootblock by allowing single cache_as_ram.S file to be used.
Change-Id: I231972982e5ca6d0c08437693edf926b0eaf9ee1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37352
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For BSP CPU, set up stack location to match the symbol from car.ld.
For AP CPUs the stack is located outside _car_region and is currently
not accounted for in the linker scripts.
Change-Id: I0ec84ae4e73ecca5034f799cdc2a5c1056ad8b74
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I83a8b2325b751feeb046ce74fabd37aeb27c28dc
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37350
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib3bf731b74cb20e886d3ecd483b37b1e3fc64ebf
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37349
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For easier C environment bootblock transition by using
already existing prototypes, BIST will not be passed
to romstage. It is expected that bootblock will have
equivalent code.
Change-Id: I0f8e3657ac79277cd77c397d1b3e931e33a6f5db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37348
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BSP and AP have two distinct execution paths for romstage.
Change-Id: Id013b165f1345509fe6b74cef2bf8c3b420f84a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I613c28a2d06f5f0216deb75960ab660941ef8057
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37044
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7dcc8d08b40560f105c22454bda1282afaa617da
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37046
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop stale comment.
Change-Id: Ie9f5271074ac4876f08fa8470dbc35daf5b694b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37053
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibe9b353ce050b4718e07bccb958dbe3d2312e741
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37045
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie1d01f589289239c453c2cc38cc1e25f903399ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37042
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibea14a4cfb7285af42a7493742636c8dc8fe0a33
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37041
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib0cd32893ad9540ae55e61e85fb03d194ee55894
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37040
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Idf522a822ddd54ee8b48312bed762c29783a2e45
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37039
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1c09eda6164efb390de4626f52aafba59962f9c4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37029
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This fixes the following:
- Fix smmstore_read_region to actually read stuff
- Clean up the code a little
- Change the loglevel for non error messages to BIOS_DEBUG
- Use an incoherent rdev to potentially speed up reading access
TESTED on google/wolf with out of tree patch to hook up smmstore to
sb/intel/lynxpoint.
Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Various recent x86 SOCs have trouble registering short pulses
generated by the H1 to indicate that it is ready for the next
transaction.
This patch adds an error message to report this condition, which would
greatly reduce the amount of guesswork when troubleshooting new
platforms.
BUG=b:144002424
TEST=tried this code on the Drallion device exhibiting the problem,
observed error messages in the coreboot log;
$ grep IRQ ap.log
Cr50 i2c TPM IRQ timeout!
Cr50 i2c TPM IRQ timeout!
Cr50 i2c TPM IRQ timeout!
Cr50 i2c TPM IRQ timeout!
...
Change-Id: I5f6ee3986bed58e12fd0ec8cecbf35f46c9263c2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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This was implemented to make sure it gets called before
attempting any PCI MMIO access. Now that we have one
central romstage_main() implementation this extra precaution
is no longer useful.
Change-Id: I09b24da827e00d7a9ba0a51d5eef36f174b893a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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The remaining (active) binaryPI boards moved away from
BINARYPI_LEGACY_WRAPPER and have POSTCAR_STAGE now.
As the cache_as_ram.S is also used with AGESA, this slightly
reduces the codesize there for romstage and postcar as well.
This commit is actually a revert for the vendorcode parts,
AMD originally shipped the codes using 'invd' for the CAR
teardown, but these were changed for coreboot due the
convoluted teardown that used to happen with non-empty stack.
Change-Id: I693c104c3aab3be537c00695cbd764a48bd603b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/18526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop all the sources that were guarded with this.
Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/19275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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It is a requirement for Firmware to have Firmware Interface Table (FIT),
which contains pointers to each microcode update.
The microcode update is loaded for all logical processors before reset vector.
FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are
input parameters to TempRamInit API.
If these values are 0, FSP will not attempt to update microcode.
Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place
hence skipping FSP-T loading ucode after CPU reset options.
Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and
CONFIG_CPU_MICROCODE_CBFS_LEN
Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kconfig became stricter on what it accepts, so accomodate before
updating to a new release.
Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Tested on OCP Mono Lake.
Change-Id: I541a23341ccce3d45239babb3f0a8a8c8542b226
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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According to IPMI SPEC, it is recommended that BIOS includes provisions
for checking and reporting on the basic health of BMC by executing
the Get Self Test Results command and checking the result.
TEST=Check the result in response data to confirm the BMC status is fine
or not.
Change-Id: I20349cec2e8e9420d177d725de2a5560d354fe47
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This was only used with amdfam10h-15h, and only in romstage
while commentary elsewhere says concurrent CMOS and CBFS
access caused issues.
We would want a cleaner approach on this, if re-implemented.
Change-Id: I8512196cb55ff2b4542b1421a1bbae540450115a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ie2e6cdddc1edb95c442a4240267fe1fd6a11d37e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36698
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia6e161c3b4fc44292cdac692a2918c522680d60d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36631
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No platform is using this.
Change-Id: I3ea6df4d9ce9043755f319f699adc189d754df1f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The MIPS architecture port has been added 5+ years ago in order to
support a Chrome OS project that ended up going nowhere. No other board
has used it since and nobody is still willing or has the expertise and
hardware to maintain it. We have decided that it has become too much of
a mainenance burden and the chance of anyone ever reviving it seems too
slim at this point. This patch eliminates all MIPS code and
MIPS-specific hacks.
Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Due to the way CAR teardown is handled in FSP 1.0, the results of
car_get_var_ptr() aren't always reliable, which can break things when
running with FMAP cache. It might be possible to fix this but would make
the code rather complicated, so let's just disable the feature on these
platforms and hope they die out soon.
Also allow this option to be used by platforms that don't have space for
the cache and want to save a little more code.
Change-Id: I7ffb1b8b08a7ca3fe8d53dc827e2c8521da064c7
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch moves the traditional POSIX stdbool.h definitions out from
stdint.h into their own file. This helps for using these definitions in
commonlib code which may be compiled in different environments. For
coreboot everything should chain-include this stuff via types.h anyway
so nothing should change.
Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Currently supports initialization, read, write, and erase operations.
Tested on HiFive Uneashed
implementation follows SD association's SPI access protocol, found
as doc http://t.cn/AiB8quFZ
Change-Id: I464d2334b8227e448c1c7e324c0455023cffb72a
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Support to display a logo using FSP 1.1 currently resides in facebook fbg1701
mainboard.
The related support is moved to drivers/intel/fsp1_1 and used by the
Facebook fbg1701 mainboard. The storage for the uncompressed logo
is changed. We don't use .bss any longer as the logo doesn't need to be
available at runtime.
BUG=N/A
TEST=booting Facebook fbg1701
Change-Id: I276e6e14fc87d0b95fe5fdf7b617afd26769de79
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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BUG=b:144297264
TEST=Boot with W25Q128JW_DTR and check MRC data save/restore works.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ica6344556e5de94555b95dd7c6df5600614811e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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This is more in line with how linker symbol for regions are defined.
Change-Id: I0bd7ae59a27909ed0fd38e6f7193816cb57e76af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch provides a chip driver for the DP-2-LVDS bridge PTN3460.
The bridge is configured via I2C. As the mainboard has all the
information regarding the attached LCD type, there are three hooks into
mainboard code to get the information like EDID data and PTN config.
TEST=Display is working on Siemens mainboards (e.g. mc_tcu3, mc_apl1, ...).
Change-Id: Ie4c8176cd16836fa5b8fd2f72faf7a55723b82f6
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The common cbmem_top_chipset implementation uses the FSP bootloader HOB,
thus move it to the fsp driver which is a more appropriate place.
Change-Id: I914df51a7414eb72416f816ff8375a13d5716925
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36620
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Provide region_device_end() and make region_end() publically available
for use to match a pattern of open coding the offset + size calculation
for both struct region and struct region_device. Apply the use of the
helpers where the usage matches in the code.
Change-Id: Iaef5d007eef9a77f7f33b0e89298abef0197352d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36689
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The FSP loops through microcode updates and at the end checks if
the microcode revision is not zero. Since we update the microcode
before loading FSP, this is the case and a fake microcode can be
passed to the FSP.
The advantage is that the Kconfig symbols to specify the location and
the size of the microcode blob can be dropped.
Change-Id: I63cfb7b19e9795da85566733fb4c1ff989e85d03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36255
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The google FSP Braswell version has broken microcode update code and
FSP checks at some point if the installed microcode version is non
zero, so coreboot has to update it before calling FSP-T.
This is fixed with newer FSP releases by Intel, but doing updates in
coreboot won't hurt.
Tested with both Intel FSP and google FSP.
Change-Id: I3e81329854e823dc66fec191adbed617bb37d649
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36198
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a property of the FSP, not something the user can decide.
Change-Id: I2086e67d39e88215ee0f124583b810f7df072f80
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I8e07c8186baf3d8e91b77c5afb731d26a1abfbaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The quotes were not stripped for the cbfs filenames of the FSP
components. This is causing problems when the regions-for-file macro is
executed (when VBOOT is enabled and the files should be filtered).
BUG=N/A
TEST=build
Change-Id: I14267502cfab5308d3874a0c0fd18a71b08bb9f8
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36548
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibc0a5f6e7be78be15f56b252be45a288b925183a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36534
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3ab62d9b1caa23305ad3b859e3c1949784ae0464
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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CONFIG_FSP_CAR should not be a user visible option, but depends on the
choice presented in the soc Kconfig.
This also removes the dependencies on ADD_FSP_BINARIES. You need to
included those for other stages too so there is no need to make this
requirement explicit for FSP-T.
Change-Id: Ida32e9c4f5839aef4d4deb7a1c7fabe6335a5d2a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Instead of doing our own calculations, rely on TOLUM returned by FSP
for cbmem_top. This (hopefully) saves us from making mistakes in weird
calculations of offsets and alignments.
Further this makes it easier to implement e.g. SGX PRMRR size selection
via Kconfig as we do not have to make any assumptions about alignments
but can simply pass (valid) values to FSP.
Tested successfully on X11SSM-F
Change-Id: If66a00d1320917bc68afb32c19db0e24c6732812
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36136
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The x86 timers are a bit of a mess. Cases where different stages use
different counters and timestamps use different counters from udelays.
The original intention was to only flip TSC_CONSTANT_RATE Kconfig
to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those
counters do run with a constant rate but we just lack tsc_freq_mhz()
implementation for three platforms.
Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a
slow run of calibrate_tsc_with_pit(). This is easy enough to fix with
followup implementation of tsc_freq_mhz() for the platforms.
Implementations with LAPIC_MONOTONIC_TIMER typically will not have
tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However,
as they don't use TSC for udelay() the slow calibrate_tsc_with_pit()
is avoided.
Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900
claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch
that romstage to use UDELAY_TSC.
Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ia8d8dc23ee0b51d62c83f5ba640b3a9aea4e744b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: Ibcb1cafe36c255b4c5bd0a4faeedb95e91048709
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ibb7b48a7a144421aff29acbb7ac30968ae5fe5ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Also, including <types.h>, is supposed to provide stdint and stddef.
Change-Id: I99918a5a77e759bc7d4192d2c3fd6ad493c70248
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I3d90e46ed391ce323436750c866a0afc3879e2e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36359
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since there are no calls where we wouldn't die(), move die() calls into
the fsp_find_* functions.
Change-Id: I750a225999688137421bbc560d9d1f5fdf68fd01
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Remove orphaned functionality from the FSP1.1 driver that only has been
used by skylake, which is now FSP2.0-only.
Change-Id: I732f2d6846788d5c03647c6fb620e45b3b66de5f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36266
Reviewed-by: Michael Niewöhner
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a function for initializing and starting FRB2 timer with the
provided countdown and action values, and a stop function for
stopping the timer.
Tested on OCP Monolake.
Change-Id: Ic91905e5f01b962473b6b3a9616266d2d95b1d6b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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RT1011 is a smart amplifier. It needs to know speaker related parameters
including speaker resistor value and temperature when the calibration is
done in order to run Dynamic Speaker Management (DSM) algorithm on chip.
The purpose of DSM is to protect speaker when the volume is large.
The calibration data of speaker is stored in VPD in factory.
This driver is needed to read data from VPD and write to ACPI _DSD when
config CHROMEOS_DSM_CALIB is turned on.
Kernel rt1011 codec driver will read these device properties to set up
codec accordingly on boot.
The reason to prepare these parameters in coreboot is because kernel
codec driver expects to read per-device parameters directly from device
properties. Another benefit is that other OS can also take these
parameters through ACPI _DSD table and take benefit of DSM on RT1011.
The kernel driver device properties of RT1011 are documented at
linux/Documentation/devicetree/bindings/sound/rt1011.txt
It is currently in ASoC maintainer's tree at
https://kernel.googlesource.com/pub/scm/linux/kernel/git/broonie/sound/+/for-next/
and hopefully should be merged to mainline kernel in the next merge window.
BUG=b:140397934
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Change-Id: I9550b9890ce2cae787f4f17779a5ade77f619171
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Avoid searching for cmos_layout.bin each time get/set_option is called
on platforms with NO_CAR_GLOBAL_MIGRATION.
Change-Id: Ie541017d2f8c8e9d4b592b71f44a08fd9670dd09
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Updated Authors file is in a separate commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia0a07df6ca1fdaa2837ce8839057057cbd44d157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Updated Authors file is in a separate commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I1acea8c975d14904b7e486dc57a1a67480a6ee6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Rename the freeranges array to better match what they represent, i.e.
ranges that are used by the current running program and CAR region that
is not unallocated.
Skip adding the CAR region if cache-as-RAM is not active.
Change-Id: I78ee5536d890f30450a5ad2a753c948b02634d6d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36110
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ida74a55b105282d86368f529cfce3523e0e97b02
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Skip calling vbt_get() if FSP is not supposed to run GOP.
Change-Id: I6b8cd3646ffcd6df39229d4e36b315dfb7a8c859
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ic90dcff9d0b49a75a26556e4a1884a2954ef68f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36063
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Add cbfsoption --ibb to mark files as IBB
* Will be used by "Legacy FIT TXT" boot
Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Change-Id: I14843c1944f2c1e0a26870b576bac549c0cac7f9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I99bc6877680b32f2bae78437ab0482baa65496d8
Signed-off-by: Greg V <greg@unrelenting.technology>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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scan_usb_bus() and root_dev_scan_bus() had the very same implementation.
So rename the latter to scan_static_bus() and use that for both cases.
Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31901
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Auto-discoverable PCI devices do not require field .enable_dev
of chip_operations to be set. They are matched with PCI drivers
by the use of PCI vendor and device ID fields.
The name given for the chip_operations struct must match the
pathname the way it is present in the devicetree.cb files. If
there was no match, util/sconfig would currently choose to
use the empty weak declaration it creates in static.c file.
Change-Id: I684a087a1f8ee4e1a5fd83450cd371fcfdbb6847
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Allow to set a lower temperature limit, as the currently hard-coded
25C may be to low for a given temperature sensor. Also enable smoo-
thing, currently hard-coded to the maximum interval of 35s, and set
the hysteresis value.
Change-Id: I5fde1cf909e8fbbaf8a345790b00c58a73c19ef8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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We accidentally converted an `int` return value to an `unsigned`,
making it impossible to check for errors with `< 0`. Fix that by
using an `int` variable.
Change-Id: I5433c27e334bc177913e138df83118b128c674b7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The existing Kconfig code made SMBIOS_PROVIDED_BY_MOBO depend
on VENDOR_LENOVO. Thus, it couldn't be selected by boards from
other vendors. So we add another Kconfig that selects it
here.
NB. It's still unclear how the two drivers in this directory
are related (at24rf08c and lenovo_serial). From the code, it
doesn't look like the latter belongs here.
Change-Id: Iaa5c5a584f2a5e2426352ec6aa681f99a55efa49
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The simple PCI config accessors are always available
under names pci_s_[read|write]_configX.
Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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We can always PCI config accessors with pci_devfn_t.
Change-Id: I6d98c2441cc870cdcadbe8fabc9f35b9ffc652d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Note that the code assumes mainboard code to configure
any PCI bridges prior to calling console_init().
Change-Id: I0312d359f153c02e4afcf1c09d79f9eb3019a8b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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ACPI 6.3, ASL 20.2.2 (Name Objects Encoding) states:
LeadNameChar := 'A'-'Z' | '_'
NameChar := DigitChar | LeadNameChar
Hence, the Intel WiFi names generated in ASL are required to be
upper-cased letters.
BUG=b:141206986
TEST=Reflash and confirmed SSDT table has correct name.
Change-Id: I803b9bc81804eec7bd5220b9dbc6ddd0bb0ecbcc
Signed-off-by: Andrew McRae <amcrae@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35466
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I68da75e3afa2f66aff9961728d4a76bc3e175fce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33527
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic90df69c27d524086405238b9683a69771c1b9d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35388
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In FSP-S, the driver constructs its pointer to UPD using the offset
in the header. Similarly, use the header's cfg_region_size for
allocating memory and copying the default configuration.
Add sanity checks for unexpedted configuration and UPD header
conditions.
TEST=Verify OK on Mandolin, verify a mock error condition
BUG=b:140648081
Change-Id: I20fad0e27a2ad537898b6d01e5241e1508da690c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Exclude FSP-M loading from the timestamps used for
RAM detection and training process.
Change-Id: I859b292f2347c6f0e3e41555ad4fb8d95a139007
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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For CML & ICL, FSP requires at least heap = 0x10000 and stack = 0x20000.
Refer to FSP integration guide to know the exact FSP requirement.
BUG=b:140268415
TEST=Build and boot CML-Hatch and ICL.
Change-Id: Ic1463181b4a9dca136d00cb2f7e3cce4f7e57bd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35301
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3323d25b72dab2f9bc8a575ba41faf059ee1ffc4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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These have become aliases to _car_global_[start|end].
Change-Id: Ibdcaaafdc0e4c6df4a795474903768230d41680d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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As code already used CBMEM hooks to switch from CAR to CBMEM
it was never necessary to have the structure declared inside
_car_relocatable_data.
Switch to use car_[get|set]_ptr is mostly for consistency, but
should also enable use of usbdebug with FSP1.0 romstage.
Change-Id: I636251085d84e52a71a1d5d27d795bb94a07422d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I03a62c6a35053b67bfc609a365068cf284bcc1a0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35265
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The documentation for StackBase and StackSize in FSPM_ARCH_UPD is
confusing. Previously the region was shared for heap and stack,
starting with FSP2.1 only for heap (or 'temporary RAM') for HOBs.
Moving the allocation outside DCACHE_BSP_STACK_SIZE allows use of
stack guards and reduces amount of reserved CAR for bootblock and
verstage, as the new allocation in .bss is only taken in romstage.
BUG=b:140268415
Change-Id: I4cffcc73a89cb97ab7759dd373196ce9753a6307
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Currently SPI vendor IDs are magic numbers in spi_flash.c. These definitions
are needed for AMD's fch_spi. So add the definitions to spi_generic.h and use
it at spi_flash.c
BUG=b:136595978
TEST=Build test of several platforms that don't use stoneyridge. Build and boot
grunt (using stoneyridge new fch_spi).
Change-Id: Ie39485d8c092151db8c9d88afaf02e19c507c93f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
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Summary:
Added a framework to search VPD in romstage before memory is
avilable. vpd_cbmem.c and vpd_premem.c are added for
code specific for premem environment and for environment that
cbmem can be used.
Since global variable is forbidden in romstage. A CAR_GLOBAL
variable is defined in vpd.c. This variable holds VPD binary
blobs' base address and size from memory mapped flash.
The overall flow is:
* The CAR variable g_vpd_blob is initialized if it was not,
either at romstage (before FSP-M execution in case of FSP UPD
customization), or at ramstage.
* At ramstage, during CBMEM_INIT, the VPD binary blob contents
are copied into CBMEM.
* At vpd_find() which may be called at romstage or at ramstage,
it sets storage for a local struct vpd_blob variable.
* The variable gets contents duplicated from g_vpd_blob, if
vpd_find() is called at romstage.
* The variable gets contents obtained from CBMEM, if vpd_find()
is called at ramstage.
Added a call vpd_get_bool(). Given a key/value pair in VPD
binary blob, and name of a bool type variable, set the variable
value if there is a match.
Several checks are in place:
* The key/value length needs to be correct.
* The key name needs to match.
* THe value is either '1' or '0'.
Test Plan:
* Build an OCP MonoLake coreboot image, flash and run.
Tags:
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iebdba59419a555147fc40391cf17cc6879d9e1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Advertise the register spacing used by the BMC as set by the Kconfig.
Tested on OCP Monolake.
Change-Id: Ib926d30f6a0e78fbf613a6f71f765c5f51eee77d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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