diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-25 18:21:05 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-27 10:41:39 +0000 |
| commit | 9266ce90c6cf6962f612b59a173149eca4e1538f (patch) | |
| tree | 1c62a7b9aef2d605d2b7c9b298a1cd8754df3228 /src/drivers | |
| parent | 56397364c9178cae527520a5fffb9eab2f6cc35b (diff) | |
AGESA,binaryPI: Remove early_all_cores()
This was implemented to make sure it gets called before
attempting any PCI MMIO access. Now that we have one
central romstage_main() implementation this extra precaution
is no longer useful.
Change-Id: I09b24da827e00d7a9ba0a51d5eef36f174b893a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/amd/agesa/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/drivers/amd/agesa/romstage.c | 12 |
2 files changed, 3 insertions, 11 deletions
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 3f1358a2f8..e3e5735c3b 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -94,8 +94,6 @@ _cache_as_ram_setup: #endif - call early_all_cores - /* Must maintain 16-byte stack alignment here. */ pushl $0x0 pushl $0x0 diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 72aac3eedd..0ecfeb2bb6 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -27,15 +27,6 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h> -#if !CONFIG(POSTCAR_STAGE) -#error "Only POSTCAR_STAGE is supported." -#endif - -void asmlinkage early_all_cores(void) -{ - amd_initmmio(); -} - void __weak platform_once(struct sysinfo *cb) { board_BeforeAgesa(cb); @@ -57,6 +48,9 @@ void *asmlinkage romstage_main(unsigned long bist) u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); int cbmem_initted = 0; + /* Enable PCI MMIO configuration. */ + amd_initmmio(); + fill_sysinfo(cb); if ((initial_apic_id == 0) && boot_cpu()) { |