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Now that the console system itself will clearly differentiate loglevels,
it is no longer necessary to explicitly add "ERROR: " in front of every
BIOS_ERR message to help it stand out more (and allow automated tooling
to grep for it). Removing all these extra .rodata characters should save
us a nice little amount of binary size.
This patch was created by running
find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';'
and doing some cursory review/cleanup on the result. Then doing the same
thing for BIOS_WARN with
's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi'
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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Support PXSX._RST and PXSX.MRST._RST for warm and cold reset.
PXSX._RST is invoked on driver removal.
build dependency:
soc/intel/common/block/pcie/rtd3
This driver will use the rtd3 methods for the same parent in the device
tree. The rtd3 chip needs to be added on the same root port in the
devicetree separately.
Test:
Add chip entry to the corresponding root port and check PXSX Device
is generated in ssdt.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61354
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The UART8250_FCR_TRIGGER bits are bits 6 and 7 in the register, so
rewrite the mask and constants as constants shifted by 6.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0663c1a641355b7bfb59f41479d17117178fb895
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib726dd77eaf1a4f8a7d9fbf8ab6d46a7bb1de6c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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UART8250_FCR_RXSR is a redefinition of UART8250_FCR_CLEAR_RCVR,
UART8250_FCR_TXSR a redefinition of UART8250_FCR_CLEAR_XMIT and
UART8250_LCR_BKSE a redefinition of UART8250_LCR_DLAB. None of those
redefinitions are used, so just drop them.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b9edae67180b04ff1c887c5742c07c774fc9c59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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The Linux kernel has the idea of an "untrusted" PCI device, which may
have limited I/O and memory access permissions, depending on which IOMMU
domains it may be a part of.
https://crrev.com/c/3406512 is a backport to the ChromiumOS kernel which
checks for this property.
BUG=b:215424986
TEST=dump SSDT on google/redrix, verify it contains the expected
UntrustedDevice property
Change-Id: I1a02ca7c5f717097ec97cf6373b9e0b81a13e05d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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The speed control bits of the Designware I2C controller are bits 1 and 2
in the control register, so the values should be written as number
shifted by the number of the first bit. The resulting constant is
identical.
TEST=Timeless build for amd/chausie results in identical binary
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0881dfcd7703ab6a70a9b1a355d5a93771aebc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This patch aligns fsp_header with the Intel specification 2.0 and 2.3.
The main impetus for this change is to make the fsp_info_header fully
accessible in soc/vendor code. Here items such as image_revision can be
checked.
TEST=verify image revision output in the coreboot serial log.
compare to FSP version shown in serial debug output.
verify Google Guybrush machine boots into OS.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: Ibf50f16b5e9793d946a95970fcdabc4c07289646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Using enum cb_err as return type instead of int improves the readability
of the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d96e5f72a8b3552ab39c1d298bafcc224bf9e55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61512
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie5c83f16146517d0aa37cd1975de725f57323094
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I2313dc209eb9035f1026a1f37ef8146c57c60986
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Outside of the designware I2C driver the generic platform_i2c_transfer
function should be used instead, so don't make dw_i2c_transfer available
outside of this file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib8b6a08b6aa2cd63adc2ef69b828661fa0ed154a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Using enum cb_err as return type instead of int improves the readability
of the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic1812c4d8d2b4d9ad331a787bd302a4f0707c1fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Using enum cb_err as return type instead of int improves the readability
of the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I55e6d93ca141b687871ceaa763bbbbe966c4b4a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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Using enum cb_err as return type instead of int improves the readability
of the code. This commit only changes the return value of the static
functions in this file keeping the external interface identical.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I80300e0b24591fc660c3134139b9257e002cdbbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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size_t is defined in stddef.h and not stdint.h, so include types.h to
get both.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3782d3a949b72d1530ebd8078c46bc695f76dc4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This will provide the definitions for size_t, uint32_t and uintptr_t.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icda8d458565bf981545d720d612cbdace04bedd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: I55682de4a1bc74f170e2044de35b0d8d53ef51ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Current max count for camera power ops is 5 which is not sufficient.
If we increase the ops by 1 in current variants the compiler
will not throw error for intel mipi camera driver.
Hence increase current max count for camera power ops to 6 from 5.
BUG=b:214665783
TEST=Build and boot to OS
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I4f4c090f2275616816dfc697f27520cd1cbc1a80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61146
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Without acpi name, acpi_device_path will return NULL.
<NULL>: Intel USB4 Retimer at GENERIC: 0.0
Replace with usb4_retimer_scope for the identify.
BUG=b:215742472
TEST=show below meaasge in coreboot log
\_SB.PCI0.TMD0.HR : Intel USB4 Retimer at GENERIC: 0.0
\_SB.PCI0.TMD1.HR : Intel USB4 Retimer at GENERIC: 0.0
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idfa8b204894409b11936e5f221c218daa206cc02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The FSP API is used to notify the FSP about different phases in the
boot process. The current FSP specification supports three notify
phases:
- Post PCI enumeration
- Ready to Boot
- End of Firmware
This patch attempts to make calling into the FSP Notify Phase APIs
optional by using native coreboot implementations to perform the
required lock down and chipset register configuration prior boot to
payload.
BUG=b:211954778
TEST=Able to build brya without any compilation issue and coreboot
log with this code changes when SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT
and SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config enabled.
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia95e9ec25ae797f2ac8e1c74145cf21e59867d64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Add driver for setting up Semtech sx9360 SAR sensor.
The driver is based on sx9310.c. The core of the driver is the same, but
the bindings are slightly different.
Registers are documented in the kernel tree:
Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
[https://patchwork.kernel.org/project/linux-iio/patch/20211213024057.3824985-4-gwendal@chromium.org/]
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Change-Id: I0a912f184e6f3501f894cca24c0d71a2c3087516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Turns out 150ms isn't enough in the worst reset conditions. On guybrush
the TPM is reset in S0i3 and the CR50 is allowed to hibernate. The CR50
is woken up and initialized early during S0i3 resume. Occasionally the
CR50 isn't ready before the probe times out.
BUG=b:213828947
BRANCH=None
TEST=suspend_stress_test -c 1000
Change-Id: Ifda438080cf1ad2796c7061223a6a97b8e6e9987
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
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FSP 2.3 specification introduces following changes:
1. FSP_INFO_HEADER changes
Updated SpecVersion from 0x22 to 0x23
Updated HeaderRevision from 5 to 6
Added ExtendedImageRevision
FSP_INFO_HEADER length changed to 0x50
2. Added FSP_NON_VOLATILE_STORAGE_HOB2
Following changes are implemented in the patch to support FSP 2.3:
- Add Kconfig option
- Update FSP build binary version info based on ExtendedImageRevision
field in header
- New NV HOB related changes will be pushed as part of another patch
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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I2C bus and address of the TPM are typically fixed on hardware so
there is no need to be able to configure this in menuconfig.
Change-Id: I1b6afa68fe753fb76348e0461209d218b14df7cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Found using:
diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<"
Change-Id: Ifad13ef418db204cf132fe00f75c6e66cd2bc51b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Found using:
diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<"
Change-Id: Ifda7b3a798c8b1736e125b2527f95e697951d7bd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Found using:
diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l 'memalign(\|malloc(\|calloc(\|free(' -- src/)
Change-Id: Id3bd3d8a2d3609a13ecbc4eab14ba745e6365cab
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The variable `custom_count` is the number of custom fields, so only
holds non-negative values, so change the struct member type from int to
size_t.
Change-Id: Ic35aafefc870092298523ba2e10adf4fcb687a01
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60790
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Building an image for OCP DeltaLake with `x86_64-linux-gnu-gcc-11` fails
with the format warning below as the size of char * differs between
32-bit and 64-bit.
CC ramstage/drivers/ipmi/ipmi_fru.o
src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_chassis_info_area':
src/drivers/ipmi/ipmi_fru.c:192:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=]
192 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for "
| ~~^
| |
| long int
| %d
193 | "chassis custom data array.\n", __func__,
194 | info->custom_count * sizeof(char *));
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| unsigned int
src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_board_info_area':
src/drivers/ipmi/ipmi_fru.c:291:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=]
291 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for "
| ~~^
| |
| long int
| %d
292 | "board custom data array.\n", __func__,
293 | info->custom_count * sizeof(char *));
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| unsigned int
src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_product_info_area':
src/drivers/ipmi/ipmi_fru.c:398:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=]
398 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for "
| ~~^
| |
| long int
| %d
399 | "product custom data array.\n", __func__,
400 | info->custom_count * sizeof(char *));
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| unsigned int
Fix the mismatches in `read_fru_chassis_info_area()` by using the length
modifier `z` for size_t as that is what `size_of` yields to.
Change-Id: If0c4266b19d56fa88abc397f305154d473ae1a93
Found-by: gcc (Debian 11.2.0-10) 11.2.0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Found using following command:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy(\|memmove(\|memset(\|memcmp(\|memchr(\|strdup(\|strconcat(\|strnlen(\|strlen(\|strchr(\|strncpy(\|strcpy(\|strcmp(\|strncmp(\|strspn(\|strcspn(\|strstr(\|strtok_r(\|strtok(\|atol(\|strrchr(\|skip_atoi(\|vsnprintf(\|snprintf(' -- src/)
Change-Id: I2a6c5b67af1d2544159e92d4b8c06cc1f5504bd2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch maps coreboot console level to FSP debug level. This
is useful to suppress MRC (FSP-M) debug logs.
Callers have to select HAVE_DEBUG_RAM_SETUP config to get verbose MRC
debug log,
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I398d576fad68a0d0fc931c175bbc04fcbc2e54ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Group all data specific to each notify phase in a struct to avoid
redundant code.
Change-Id: Ib4ab3d87edfcd5426ce35c168cbb780ade87290e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Sort includes alphabetically, drop spaces after type casts and unbreak
some long lines that are less than 96 characters long.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I2dafd677abbdd892745fea1bf4414f6e0d5549bb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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When coreboot goes to die because FSP returned an error, log the return
value in the message printed by `die()` or `die_with_post_code()`.
Change-Id: I6b9ea60534a20429f15132007c1f5770760481af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>,
<stdbool.h>, <stdint.h> and <stddef.h> headers.
Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Replace `Decrement (a)` with `a--`.
Change-Id: I45c3d339652dd457cd4664ed03123eee2d7a5684
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
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Replace `Increment(a)` with `a++`.
Change-Id: If0c11f43713bf7afec6dd600289776eefd1331e8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `LOr (a, b)` with `a || b`.
Change-Id: I26f785c2f959539141e70053ae38aac16d3b9185
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
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Replace `Divide (a, b)` with `a / b`.
Change-Id: Icfae760441560e1aa51383d04a3898412ba1be04
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60571
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Replace `Multiply (a, b)` with `a * b`.
Change-Id: Idd77fa995e1edab86c509a88a1ba16d636c60b30
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
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Replace `Add (a, b)` with `a + b`.
Change-Id: I9d9f1d04f39ffd420655d9297b01b8811339ad08
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Replace `Subtract (a, b)` with `a - b`.
Change-Id: I4f6ffd6bbf6a37e041879e50fe41ce3cc856371f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace Index(FOO, 1337) with FOO[1337].
Change-Id: I534c1581e587908feeb06fd7725c5895649dcfb1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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The Realtek RTL8125 has four registers for four leds
and a feature config register.
We use led0 and led2 in brask, so modify ethernet driver.
Those registers' IO address are based on RTL8125 datasheet.
BUG=b:193750191
TEST=Modify overridetree.cb to verify LEDs' settings.
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com>
Change-Id: I4b05a859dc0a0d2b8d6b35d6491fc88f7077cb92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Currently, the pmc_mux/conn driver uses integer fields to store the
USB-2 and USB-3 port numbers from the SoC's point of view. Specifying
these as integers in the devicetree is error-prone, and this
information can instead be represented using pointers to the USB-2 and
USB-3 devices. The port numbers can then be obtained from the paths of
the linked devices, i.e. dev->path.usb.port_id.
Modify the driver to store device pointers instead of integer port
numbers, and update all devicetrees using the driver. These are the
mainboards affected (all are Intel TGL or ADL based):
google/brya
google/volteer
intel/adlrvp
intel/shadowmountain
intel/tglrvp
system76/darp7
system76/galp5
system76/lemp10
Command used to update the devicetrees:
git grep -l "usb._port_number" src/mainboard/ | \
xargs sed -i \
-e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \
-e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g'
BUG=b:208502191
TEST=Build test all affected boards. On brya0, boot device and check
that the ACPI tables generated with and without the change are the same.
Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The Bayhub LV2 has a known errata wherein PCI config registers at
offsets 0x234, 0x238, and 0x24C will only correctly accept writes
when they are addressed via a DWORD (32-bit) wide write operation
on the PCIe bus. Offset 0x234 is the LTR max snoop and max no-snoop
latency register, therefore add a finalize callback to this driver
which will program the LTR max-snoop/no-snoop register with a 32-bit
write using the values from pciexp_get_ltr_max_latencies().
BUG=b:204343849
TEST=verified the PCI config space writes took effect on google/taeko
Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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This should make it a bit clearer what the differences between
SPI_CNTRLR_DEDUCT_OPCODE_LEN and SPI_CNTRLR_DEDUCT_CMD_LEN and the
corresponding functionality in spi_crop_chunk are.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I809adebb182fc0866b93372b5b486117176da388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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In the case of deduct_cmd_len being set and the adjusted cmd_len >=
ctrlr_max, ctrlr_max wasn't being adjusted and still had the value of
ctrlr->max_xfer_size. Handle this edge case (which we should never run
into) by setting ctrlr_max to 0 and printing a warning to the console.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9941b2947bb0a44dfae8ee69f509795dfb0cb241
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Currently coreboot interprets TCSS port number as per physical port
number while EC abstracts port number and provides indices as port
number. For example, if TCSS port 1 and 3 are enabled on the board,
coreboot will interpret port numbers as 0 and 2, but since only 2 ports
are enabled in the system EC will assign port numbers as 0 and 1.
This creates a port number mismatch while communicating between EC and
coreboot. This patch addresses issue where SoC can implement function
to map correct EC port as per port enabled in mainboard.
BUG=b:207057940
BRANCH=None
TEST=Check if code compiles successfully. Functionality will work once
function is implemented in SoC code.
Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add entry in ACPI table under IPU device to provide silicon type
information to IPU driver. IPU kernel driver can decide the type of
firmware to load based on this information.
BUG=b:207721978
BRANCH=none
TEST=Check for the ACPI entry in the SSDT after booting to kernel
Change-Id: I4e0af1dd50b9c014cae5454fcd4f9f76d0e0a85f
Cq-Depend: chromium:3319905
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The Realtek RT8168 and RT8125 have a similar programming interface,
therefore add the PCI device ID for the RT8125 into driver for support.
BUG=b:193750191
TEST=emerge-brask coreboot chromeos-bootimage. Test on brask whose NIC
is RT8125. Check if the default MAC is written into the NIC.
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Utilize retry() macro in wait_aux_op_finish() and anx7625_init() to
simplify the code.
BUG=none
TEST=emerge-asurada coreboot
BRANCH=none
Change-Id: I207e7075e8ac905efd5f201dd54658dedf531568
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
The current implementations of edid_read() and segments_edid_read() have
a few problems:
1. The type of variable `c` is incorrect, not matching the return type
of sp_tx_aux_rd(). In addition, the meaning of `c` is unknown.
2. It is pointless to do `cnt++` when sp_tx_aux_rd() fails.
3. These two functions ignore the return value of
anx7625_reg_block_read().
4. In segments_edid_read(), anx7625_reg_write() might return a positive
value on failure.
Fix all of the 4 issues, and modify the code to be closer to kernel
5.10's implementation (drivers/gpu/drm/bridge/analogix/anx7625.c). Note
that, however, unlike in kernel, anx7625_reg_block_read() here doesn't
return the number of bytes. On success, 0 is returned instead.
In addition, following coreboot's convention, always return negative
error codes. In particular, change the return value to -1 for
edid_read() and segments_edid_read() on failure.
BUG=b:207055969
TEST=emerge-asurada coreboot
BRANCH=none
Change-Id: Ife9d7d97df2926b4581ba519a152c9efed8cd969
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Some boards may want to use a _HID instead of an _ADR to locate a
graphics device. This patch provides that option in the devicetree.
BUG=b:206850071
TEST=Add `hid` entry in devicetree, dump SSDT and see _HID instead of
_ADR
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I32be4abf5c60be1f94aabaa2e9c734215c4e291e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The SMMSTORE_IN_CBFS option was just meant as a workaround for an
attempt to backport SMMSTORE into older Chromebooks that never actually
happened. All current and future users of coreboot should be using
SMMSTORE in an FMAP region. The APIs needed for SMMSTORE_IN_CBFS clash
with the CBFS rdev isolation needed for CBFS_VERIFICATION, so let's just
get rid of it.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia0604a4ffd20b46774631d585925311b65d5a0e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59680
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Some boards may use more than 4 temperature sensors for DPTF thermal
control, so this patch adds support for one more temperature sensor.
BUG=b:207585491
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibf9666bade23b9bb4f740c6c4df6ecf5227cfb45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
CB:59479 introduced a blank default statement. This is treated as an
error or warning on some older toolchains. Add a break statement on
default case.
BUG=None
TEST=Build the Guybrush mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3d034cfebc8b8ae7d7024d41b4b2207cdeb083e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
|
The device is a PCIe Gen1 to SD 3.0 card reader controller to be
used in the Chromebook. The datasheet name is GL9750S and the revision
is 01.
The patch disables ASPM L0s.
BUG=b:206014046
TEST=Verify GL9750 enters L1 by observing CLKREQ# de-asserts.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Introduce firmware-power-managed DSD ACPI property for TPM devices.
This property can be checked by the kernel TPM driver to override how
the TPM power states are managed. This is a tri-state flag, true,
false, or unset. So an enum used to keep the flag is unset by default.
When firmware-power-managed is true, the kernel driver will not send a
shutdown during s2idle/s0i3 suspend.
BUG=b:200578885
BRANCH=None
TEST=TPM shutdown is triggered on s0ix suspend on guybrush with patched
kernel
Change-Id: Ia48ead856fc0c6e637a2e07a5ecc58423f599c5b
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
There seems to be no operational differences between x86 and PPC64 for
UART 8250. Port number is the same. References:
* https://github.com/open-power/docs/issues/25
* https://github.com/3mdeb/openpower-coreboot-docs/blob/main/devnotes/porting.md#enabling-console
Tested on Talos II (https://raptorcs.com/TALOSII/). Works in QEMU as
well (actually in QEMU it works even without this change somehow).
Change-Id: Ib06001076b8eaa577a8d2159afea20afb610687d
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
The _DSC (Device State for Configuration) object evaluates to an integer
may be used to tell Linux the highest allowed D state for a device
during probe. The support for _DSC requires support from the kernel
bus type if the bus driver normally sets the device in D0 state for
probe.
The D states and thus also the allowed values for _DSC are listed below.
Number State Description
0 D0 Device fully powered on
1 D1
2 D2
3 D3hot
4 D3cold Off
More details can be found here https://lkml.org/lkml/2021/10/25/397
BUG=none
BRANCH=none
TEST=Add corresponding field in brya, boot and dump SSDT to check if
_DSC field is as per expectation.
Name (_ADR, Zero) // _ADR: Address
Name (_HID, "OVTI8856") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_DDN, "Ov 8856 Camera") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Method (_DSC, 0, NotSerialized)
{
Return (0x04)
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I65a83fcd69296f13c63329701ba9ce53f7cc2cb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
So far POST codes were mapped on IO port 0x80 inside the NC FPGA which
was connected via the LPC bus to the host CPU. On recent x86 generations
the LPC bus was replaced with eSPI and not all Siemens boards have the
eSPI routed to the NC FPGA. In order to have POST codes visible on those
boards the display is accessible via PCI in addition.
This patch adds the feature of sending the POST codes to the NC FPGA via
a PCI mapped register.
Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
|
|
Change to use MAX_DSAR_SET_COUNT which WLAN driver always expects 3
no matter what the revision is for EWRD.
It will pass the WLAN driver check then to retrieve the data properly.
BUG=b:204414616
TEST= tested on brya with DRTU tool to verify if SAR table is
read properly or not.
Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8
Signed-off-by: Matt Chen <matt.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The APs don't execute this codepath but ap_romstage_main().
Change-Id: If884001bc8c5363efbbf00422a9a700896318f7b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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In the non-XIP world, FSP is normally memmapped and then decompressed.
The AMD SPI DMA controller can actually read faster than mmap. So by
reading the contents into a buffer and then decompressing we reduce boot
time.
BUG=b:179699789
TEST=Boot guybrush and see 30ms reduction in boot time
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This option will allow setting the FSP alignment in CBFS.
BUG=b:179699789
TEST=Boot with and without the option set and verify -a option was
passed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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AMD platforms pass in the base address to cbfs tool:
fspm.bin-options: -b $(CONFIG_FSP_M_ADDR)
There is no technical reason not to allow FSP-M to be relocated when
!XIP. By allowing this, we no longer need to pass in the base address
into cbfstool when adding fspm.bin. This enables passing in the
`--alignment` argument to cbfs tool instead. cbfstool currently has a
check that prevents both `-b` and `-a` from being passed in.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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elog init requires doing a lot of SPI transactions. This change makes it
clear how long we spend initializing elog.
BUG=b:179699789
TEST=Boot guybrush and see elog init timestamps
114:started elog init 3,029,116 (88)
115:finished elog init 3,071,281 (42,165)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia92372dd76535e06eb3b8a08b53e80ddb38b7a8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58957
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.
Change-Id: Ia9a4b62c857f7362d67aee4f9de3bb2da1838394
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Add backlight support in ps8640 through the AUX channel using eDP
DPCD registers.
BUG=b:202966352
BRANCH=trogdor
TEST=verified firmware screen works on homestar rev4
Change-Id: Ief1bf56c89c8215427dcbddfc67e8bcd4c3607d2
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
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commit 6af980a2a
(drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially)
drops CB_SUCCESS check for mp_run_on_all_aps function hence, this
changes bring back the required return type against CB_SUCCESS.
Change-Id: I9fc81e6a7eebbf0072ea2acb36b3c33539b517a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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As per MP service specification, EDK2 is allowed to specify the mode
in which a 'func' routine should be executed on APs.
`SingleThread` sets to 'true' meaning to execute the function one by
one (serially) or sets to 'false' meaning to execute the function
simultaneously.
MP service API `StartupAllAPs` was designed to pass such options as
part of function argument.
But another MP service API `StartupAllCPUs` doesn't specify any such
requirement. Running the `func` simultaneously on APs results in
a coherency issue (hang while executing `func`) due to lack of
acquiring a spin lock while accessing common data structure in
multiprocessor environment.
BUG=b:199246420
Change-Id: Ia95d11408f663212fd40daa9fd9b0881a07f1ce7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Not all platforms need to generate power resources, but the code does
not get optimized out at build time because the devicetree gets
compiled into a linked list. As this code pulls in some heavy ACPI
dependencies that is even implemented with weak empty function it
makes sense to optimize out this code using a Kconfig constant.
This saves 1.5K in ramstage size on gigabyte/ga-945gcm-s2l.
Change-Id: I82289aa7e6e82318417f3b827b86182891dfc2a6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58657
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use %u instead of %d for printing unsigned variables.
Change-Id: I0f4bf7b80dfbde0802af8ad96fd553cb75d60e6e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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There are manual timeout-loops which use a fixed value and udelay().
In all cases there is a debug printk() inside this loop which, when
enabled, takes way longer than the counted microsecond delay. This
leads to the result that e.g. a 1 second delay takes nearly an eternity
if the debug messages are enabled due to the longer function execution
time.
This patch uses the stopwatch scheme for the timeout-loops which still
makes sure that the timeout period is maintained while it takes longer
function calls like printk() into account. In order to keep the minimum
delay between two register accesses on the TPM keep the udelay(1)-call.
TEST=Enable TPM debug messages on a board where the TPM hits a timeout
by failure and make sure that the debug messages occur in the log
just in the timeout period. It still works as expected if the debug
messages are disabled.
Change-Id: I8fd261c9d60a9a60509c847dbc4983bc05f41d48
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps,
mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the
different return values. This patch also adds the types.h include that
provides the definition of the cb_err enum and checks the return value
of all 4 functions listed above against the enum values instead of
either checking if it's non-zero or less than zero to handle the error
case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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All boards with DRIVERS_GENERIC_IOAPIC select it.
Presumably the related configuration of routing IRQ0 when
IOAPIC is enabled should be always done to provide i8259
legacy compatibility for payloads.
Change-Id: Ie87816271fa63bba892c8615aa5e72ee68f6ba93
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: Ie3c820e2e20f8f71908319e89e49e5d66f58adc9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
There is the wrong register offset printed in the debug log when the
data register is written:
'lpc_tpm: Write reg 0x18 with 0xnn' should be
'lpc_tpm: Write reg 0x24 with 0xnn' for data FIFO access.
This can be confusing when searching for issues with the help of the
TPM debug messages since the code itself is correct. Fix this error.
Change-Id: Ic28ee5a07146e804574b887ea05c62e7e88e9078
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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|
Return the package with a value for the dptf user space service.
This is required in write tpch method for pch device under dptf
driver.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I64e1bb04a6115c7f93c84a5d6644101ac1d3d8ba
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add various methods support for pch device under dptf driver.
This provides support of different control knobs for FIVR.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Some distributions (e.g. NixOS, Debian) are actively working on getting
rid of EOL Python 2. Since `SplitFspBin.py` supports both Python 2 and
Python 3 as of upstream commit 0bc2b07, use whatever version is present
by utilizing `python`.
Change-Id: I2a657d0d4fc1899266a9574cfdfec1380828d72d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds type-c port information for USB type-c ports to cbmem.
BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot
volteer2 to kernel, log in and check cbmem for type-c info exported to
the payload:
localhost ~ # cbmem -c | grep type-c
added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0
Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Move the locally declared typec_orientation enum from chip.h to
coreboot_tables.h.
Change enum typec_orientation name to type_c_orientation for consistency
with contents of coreboot_tables.h.
Rename TYPEC_ORIENTATION_FOLLOW_CC to TYPEC_ORIENTATION_NONE.
BUG=b:149830546
TEST="emerge-volteer coreboot" and make sure it compiles successfully.
Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
On AArch64 platforms, GIC initialization is generally the job of Trusted
Firmware and shouldn't be necessary in coreboot. Only the ancient T210
platform (which was started before we had decided on using Trusted
Firmware) calls this code, and even there they have a comment wondering
"do we still need this?". I'm just gonna assume (without testing because
that board is ancient and I'm lazy) that they don't, and that the TF GIC
initialization[1] is sufficient here. Remove this obsolete driver.
[1] https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ff448/plat/nvidia/tegra/soc/t210/plat_setup.c#259
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
When the entry delay of L0s is less than the entry delay of L1, GL9755
will enter L0s state first. When it exits from L0s state, the time of L1
entry will be reset. Therefore, the conditions for entering L1 state
cannot be met. In order to enter L1 state, L0s needs to be disabled.
BUG=b:195611000
TEST=Verify GL9755 enters L1 by observing CLKREQ# de-asserts.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: If121b5cb534eb32bac8992683c3f0eee8946acec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This change drops the function `find_gfx_dev()` as it is unused now.
Change-Id: Ie42707bd45348dc7485ca0ca12ebff2994897e6b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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Add two properties (maxim, vmon-slot-no/maxim, imon-slot-no) in maxim9839 driver.
This is I/V source destination definition that from below properties .
maxim,vmon-slot-no => PCM_IVADC_V_DEST
maxim,imon-slot-no => PCM_IVADC_I_DEST
BUG=b:197076844
TEST=build and check SSDT
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Idb24d19c7cfea559bf6d53f401d66cadb8b3acc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This include provides the definition of enum cb_err.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idfee720de920377796e3fd64cb47514b8cb08c34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
smp_processor_id is defined in src/arch/arm64/include/armv8/arch/cpu.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0b610189bf439774cb900f74559dee314cbc5854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Add mipi panel support for wormdingler
- Add the following panel for wormdingler:
INX P110ZZD-DF0
BOE TV110C9M-LL0
- Use panel_id to distinguish which mipi panel to use.
- Setup panel orientation
BUG=b:195898400,b:198548221
BRANCH=none
TEST=emerge-strongbad coreboot
Change-Id: I8cd28e024ecbfdcd473bc39efb529eb4aca1b5d0
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
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FspMultiPhaseSiInit API was introduced with FSP 2.2 specification
onwards. EnableMultiPhaseSiliconInit is an arch UPD also introduced
as part of FSP 2.2 specification to allow calling FspMultiPhaseSiInit
API.
However, some platforms adhere to the FSP specification but
don't have arch UPD structure, for example : JSL, TGL and Xeon-SP.
Out of these platforms, TGL supports calling of FspMultiPhaseSiInit
API and considered EnableMultiPhaseSiliconInit as a platform-specific
UPD rather than an arch UPD to allow calling into FspMultiPhaseSiInit
API.
It is important to ensure that the UPD setting and the callback for
MultiPhaseInit are kept in sync, else it could result in broken
behavior e.g. a hang is seen in FSP if EnableMultiPhaseSiliconInit
UPD is set to 1 but the FspMultiPhaseSiInit API call is skipped.
This patch provides an option for users to choose to bypass calling
into MultiPhaseSiInit API and ensures the EnableMultiPhaseSiliconInit
UPD is set to its default state as `disable` so that FSP-S don't
consider MultiPhaseSiInit API is a mandatory entry point prior to
calling other FSP API entry points.
List of changes:
1. Add `FSPS_HAS_ARCH_UPD` Kconfig for SoC to select if
`FSPS_ARCH_UPD` structure is part of `FSPS_UPD` structure.
2. Drop `soc_fsp_multi_phase_init_is_enable()` from JSL and Xeon-SP
SoCs, a SoC override to callout that SoC doesn't support calling
MultiPhase Si Init is no longer required.
3. Add `FSPS_USE_MULTI_PHASE_INIT` Kconfig for SoC to specify if
SoC users want to enable `EnableMultiPhaseSiliconInit` arch UPD (using
`fsp_fill_common_arch_params()`) and execute FspMultiPhaseSiInit() API.
4. Presently selects `FSPS_USE_MULTI_PHASE_INIT` from IA TCSS common
code.
5. Add `fsp_is_multi_phase_init_enabled()` that check applicability of
MultiPhase Si Init prior calling FspMultiPhaseSiInit() API to
honor SoC users' decision.
6. Drop `arch_silicon_init_params()` from SoC as FSP driver (FSP 2.2)
would check the applicability of MultiPhase Si Init prior calling
FspMultiPhaseSiInit() API.
Additionally, selects FSPS_HAS_ARCH_UPD for Alder Lake as Alder Lake
FSPS_UPD structure has `FSPS_ARCH_UPD` structure and drops
`arch_silicon_init_params()` from SoC
`platform_fsp_silicon_init_params_cb()`.
Skip EnableMultiPhaseSiliconInit hardcoding for Tiger Lake and uses
the fsp_is_multi_phase_init_enabled() function to override
EnableMultiPhaseSiliconInit UPD prior calling MultiPhaseSiInit FSP API.
TEST=EnableMultiPhaseSiliconInit UPD is getting set or reset based on
SoC user selects FSPS_USE_MULTI_PHASE_INIT Kconfig.
Change-Id: I019fa8364605f5061d56e2d80b20e1a91857c423
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Instead of always passing LB_FB_ORIENTATION_NORMAL, allow the chipsets
implementing the callback to pass in an orientation.
BUG=b:194967458
BRANCH=dedede
Change-Id: I4aacab9449930a75aca9d68bf30d019f86035405
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Maxim driver look for "maxim,dsm_param_name" to load dsm parameter file.
dsm param file name consist of {dsm_param_file_name} filled in devicetree,
{MAINBOARD_VENDOR} and {MAINBOARD_PART_NUMBER}.
=> {dsm_param_file_name}_{MAINBOARD_VENDOR}_{MAINBOARD_PART_NUMBER}.bin
BUG=b:197076844
TEST=build, and check ssdt
Change-Id: I006572d6a6ea55298374c688dfd9d877835da82d
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The call to the `get_smbios_data` device operation is followed by
calls to unconditional default functions, which lacks flexibility.
Instead, have devices that implement `get_smbios_data` call these
default functions as needed.
Most `get_smbios_data` implementations are in mainboard code, and are
bound to the root device. The default functions only operate with PCI
devices because of the `dev->path.type != DEVICE_PATH_PCI` checks, so
calling these functions for non-PCI devices is unnecessary. QEMU also
implements `get_smbios_data` but binds it to the domain device, which
isn't PCI either.
Change-Id: Iefbf072b1203d04a98c9d26a30f22cfebe769eb4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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