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2019-11-29drivers/pc80/pc/i8254.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans
Change-Id: Ibe9b353ce050b4718e07bccb958dbe3d2312e741 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37045 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29security/tpm: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans
Change-Id: I1c09eda6164efb390de4626f52aafba59962f9c4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37029 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22drivers/pc80/rtc: Remove CMOS spinlockKyösti Mälkki
This was only used with amdfam10h-15h, and only in romstage while commentary elsewhere says concurrent CMOS and CBFS access caused issues. We would want a cleaner approach on this, if re-implemented. Change-Id: I8512196cb55ff2b4542b1421a1bbae540450115a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-21drivers/pc80/tpm: Replace __RAMSTAGE_ guardsKyösti Mälkki
Change-Id: Ia6e161c3b4fc44292cdac692a2918c522680d60d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36631 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05drivers/pc80: Remove UDELAY_TIMER2Kyösti Mälkki
Change-Id: Ibc0a5f6e7be78be15f56b252be45a288b925183a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36534 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05drivers/pc80: Remove UDELAY_IOKyösti Mälkki
Change-Id: I3ab62d9b1caa23305ad3b859e3c1949784ae0464 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-11-03cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki
The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-02cpu/x86: Move calibrate_tsc_with_pit() to drivers/pc80Kyösti Mälkki
Change-Id: Ia8d8dc23ee0b51d62c83f5ba640b3a9aea4e744b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-10-27src/[arch-lib]: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibb7b48a7a144421aff29acbb7ac30968ae5fe5ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/36329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27src: Use 'include <boot/coreboot_tables.h>' when appropriateElyes HAOUAS
Change-Id: I3d90e46ed391ce323436750c866a0afc3879e2e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36359 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-23drivers/pc80/rtc: Avoid searching for cmos_layout.bin on each get/set_optionArthur Heymans
Avoid searching for cmos_layout.bin each time get/set_option is called on platforms with NO_CAR_GLOBAL_MIGRATION. Change-Id: Ie541017d2f8c8e9d4b592b71f44a08fd9670dd09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-22AUTHORS: Move src/drivers/[l*-v*] copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Updated Authors file is in a separate commit. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia0a07df6ca1fdaa2837ce8839057057cbd44d157 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-13drivers/pc80: Remove some __PRE_RAM__ and __SMM__Kyösti Mälkki
Change-Id: Ic90df69c27d524086405238b9683a69771c1b9d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35388 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08drivers/pc80: Move UDELAY_IO and UDELAY_TIMER2Kyösti Mälkki
No longer fallback to UDELAY_IO as default. Since these are not cpu properties or features, move the Kconfig location. Change-Id: I9809cdc285c7bf741aa391ddb5755390bbfc2909 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-02drivers/pc80/rtc/mc146818rtc_boot: Use size_t for lengthElyes HAOUAS
Change-Id: I877e19c014759e33b9cc48ff9ee27e898737aece Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-27drivers/pc80/tpm: add support for TPM emulator SwTPM 2.0 moduleTsung Ho Wu
Add software TPM 2.0 emulator to tpm device probe list. SwTPM: https://github.com/stefanberger/swtpm Tested on qemu q35 with MAINBOARD_HAS_LPC_TPM and MAINBOARD_HAS_TPM2 set in qemu-q35 Kconfig. Qemu: see qemu flags at https://s3hh.wordpress.com/2018/06/03/tpm-2-0-in-qemu/ How to see it work. Ubuntu 18.04: 1. Install SwTPM from https://github.com/stefanberger/swtpm 2. Add MAINBOARD_HAS_LPC_TPM and MAINBOARD_HAS_TPM2 to src/mainboard/emulation/qemu-q35/Kconfig and rebuild coreboot.rom 3. mkdir -p swtpm0 4. swtpm socket --tpmstate dir=swtpm0 --tpm2 --ctrl \ type=unixio,path=swtpm0/swtpm-sock --log level=20 & 5. qemu-system-x86_64 -machine q35 -m 2G \ -chardev socket,id=chrtpm,path=swtpm0/swtpm-sock \ -tpmdev emulator,id=tpm0,chardev=chrtpm -device \ tpm-tis,tpmdev=tpm0 -pflash build/coreboot.rom \ -serial $(tty) -display none 6. Check boot log and search 'Found TPM'. Change-Id: I5f58d2c117afbd057bb91697912db826db1d67a1 Signed-off-by: Tsung Ho Wu <tsungho.wu@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33302 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29src/{device,drivers}: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I3395715f9e2b03175089186ab2e57d9e508fc87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-06Fix code that would trip -Wtype-limitsJulius Werner
This patch fixes up all code that would throw a -Wtype-limits warning. This sometimes involves eliminating unnecessary checks, adding a few odd but harmless casts or just pragma'ing out the warning for a whole file -- I tried to find the path of least resistance. I think the overall benefit of the warning outweighs the occasional weirdness. Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-05drivers/pc80/rtc/mc146818rtc.c: Reset RTC time on RTC power failureFrans Hendriks
RTC time contains invalid values on system without RTC battery. Handle 'invalid' the same way as 'cmos_invalid'. This will reset CMOS date when calling function enables 'invalid'. BUG=N/A TEST=Portwell PQ-M107 booting Linux Embedded Change-Id: I5eae57d00f328400a8b03c28b7ecdbbc71522206 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29329 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-25Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-08drivers/keyboard: Fix spelling of *interface*Paul Menzel
`git grep iterface` shows that these are the only two occurrences. Change-Id: I838a60c95c5d0fc3dee902f0b72761dd60c36221 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/31286 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23src/drivers: Remove needless '&' on function pointersElyes HAOUAS
Change-Id: I7a99d0dcbc8ea1362a12a68fa519c49058d30a05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-09drivers/*/tpm: Add postcar targetPhilipp Deppenwiese
Now postcar is a standalone stage, add it as target to all TPM bus drivers. This is a required for a measured boot. Change-Id: I758185daf3941a29883c2256b900360e112275e1 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/29546 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-29src/drivers/pc80/tpm/tis.c: Dont use port value when invalid.Frans Hendriks
port is allocated in ACPI, without checking for value. Don't use port value when zero. BUG=N/A TEST=Portwell PQ-M107 Change-Id: Ia44281b82d003b29bffbf985b774ddd661b65c4e Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/29331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-08-28src/drivers/pc80/pc: Remove unneeded includeElyes HAOUAS
Change-Id: Ic238181d5c26ab8cf549137824a7c5e6c6d80ab1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20drivers/pc80/rtc: do not warn if CMOS options are unavailableStefan Tauner
Callers should have a default ready and get noticed by the return value of get_option(). No need to scare log readers at this location. Change-Id: Ied373d8a02afdc8d1017c9f41d9004e3797dfbb3 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28215 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-11drivers/pc80/tpm: add support for SLB9665 TPM2.0 moduleKamil Wcislo
SLB9665 are not initialized correctly. It looks like SLB9665 and SLB9660 return the same DEV ID. Initialize these devices according to TPM Kconfig selections. Tested on apu2 with following change: https://review.coreboot.org/#/c/coreboot/+/28000/ Change-Id: Ic20b9a65ef6a4ee392a9352f7c9bf01b2496f482 Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/21983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-10src/drivers: Fix typoElyes HAOUAS
Change-Id: I9144937b72a98517cbd41c093cff7bad543b4140 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27916 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-09src/{device,drivers}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ic1c9b1edd8d3206a68854107ddcbc5c51cb487c3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-03drivers/pc80/vga: Fix coding styleElyes HAOUAS
Change-Id: I0452407d1346ca8ead2638e2a31269931ea5d12e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-28vboot: Fix linking error with USE_OPTION_TABLE enabledPatrick Rudolph
Fix a linking problem with VBOOT and USE_OPTION_TABLE enabled. Make use of cbfs_locate_file_in_region() and always search the cmos_layout.bin in the 'COREBOOT' region. With this change applied there's no need to include the vboot_locator in SMM any more, we can't break NVRAM with different CMOS layouts, and we keep VBOOT and non VBOOT behaviour the same. Only include cmos_layout.bin and cmos.default in RO region. Add notes explaining the decisions. Tested on Intel Sandybridge, builds and boots with vboot enabled. Change-Id: I10ae94d7936581bbb5ea49384122062bd4934ea5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-13drivers/pc80/tpm: get ioport from pnp recordsKevin Cody-Little
Had 0x2e hardcoded, which is often the SuperIO chip. Instead, pull the port from the PNP tree generated from devicetree.cb, where either 0x4e or 0x2e will be specified. Change-Id: I4a92693f8acd3a1618cefcdf6b25eb22a727e20f Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16drivers/pc80/tpm: Add some optional delay to tis_readresponse()Bill XIE
Certain TPMs (observed on Infineon SLB9635 installed on revolve 810 g1) seem to need some delay between tis_wait_valid() and tis_has_valid_data(), or tis_has_valid_data() may invalidly return 0, ending the loop immaturely with some bytes left unread, and fail to pass the check below, causing the current command not finalized by tis_command_ready(), and blocking any later tis_wait_ready(). This time the added delay is controlled by a Kconfig option TPM_RDRESP_NEED_DELAY. Change-Id: Ic2a2f252e72a0bbce51e2863f8e46647b1570ba5 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/25322 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-14drivers/pc80/tpm: Remove unused ACPI opregionDuncan Laurie
The opregion and fields are left over from when ACPI ASL code was reading registers to determine the current setup. Now that the ACPI device is generated with the correct information already this code is not used at all and can be removed from the tree. Change-Id: If89d90cc7105ed21e2134ac99224f6f8214cc8ad Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/22854 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-20vboot: remove init_vbnv_cmos()Aaron Durbin
Instead of having each potential caller deal with the differences of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the correct logic within the callee, cmos_init(), for handling the vbnv in CMOS. The internal __cmos_init() routine returns when the CMOS area was cleared. BUG=b:63054105 Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21549 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-14device: acpi_name() should take a const struct deviceAaron Durbin
There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-28src/drivers: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
This excludes files which are mostly spaces, which I felt should be handled separately. Change-Id: I33043a3090e2fc6e9d2fd81e8a5e46fb6cb0aa35 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-07-26Port cmos.default handling to C environment bootblockNico Huber
Gather related code in the new file drivers/pc80/rtc/mc146818rtc_boot.c, call sanitize_cmos() from C environment bootblock. Change-Id: Ia5c64de208a5986299c0508d0e11eeb8473deef1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-26drivers/pc80/rtc: Build for bootblock and postcar stages tooNico Huber
Fixes builds with BOOTBLOCK_CONSOLE && USE_OPTION_TABLE. Change-Id: I1c7e9baa60f33c2c3651e2def0335454f7e20451 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13src/drivers: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Ib3a1cf04482a8f19b159c31cfb16a7b492748d91 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-05-22Kconfig: Move and clean up CONFIG_VGANico Huber
Change-Id: I6e710b95cade0ea68f787f33c0070613d64b6da6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-05-13drivers/pc80/rtc: Rename mc146818rtc_early.c -> _romcc.cNico Huber
And don't link it. It's for ROMCC. To make code happy that uses the ROMCC interface read_option(), read_option_lowlevel() is ported to mc146818rtc.c along with a message to use get_option() instead. Change-Id: I54ea08de034766c8140b320075d36d5e811582fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-05drivers/pc80/tpm: Fix missing tis_close() functionPhilipp Deppenwiese
tis_close() must be called after tis_open() otherwise the locked locality isn't released and the sessions hangs. Tested=PC Engines APU2 Change-Id: I1a06f6a29015708e4bc1de6e6678827c28b84e98 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/19535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-04-24*.asl: Remove obsolete reference to TPM ASL filePatrick Rudolph
TPM ACPI entries are automatically generated, and the old static TPM ASL file is obsolete. Remove the reference to this obsolete static and empty ASL file. Delete src/drivers/pc80/tpm/acpi/tpm.asl. Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20src/drivers/pc80: Update vga_font_8x16.c to be non-binaryMartin Roth
Previously, the file -i command identified vga_font_8x16.c as application/octet-stream; charset=binary Now it identifies as: text/x-c; charset=us-ascii - Remove non-ascii characters Change-Id: I6b513e6457a31828a6e94c954a7e2e7ee18fd4d6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18372 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-02-14drivers/pc80/tpm: Update default acpi pathTobias Diedrich
The existing default path of PCI0.LPCB is missing the \_SB prefix and prevents Linux from detecting the TPM. This is assuming that normally the LPCB device is most commonly on \_SB.PCI0.LPCB. SSDT excerpt without the patch: """ DefinitionBlock ("", "SSDT", 2, "CORE ", "COREBOOT", 0x0000002A) { External (_SB_.PCI0.GFX0, DeviceObj) [...] External (_SB_.PCI0.SATA, DeviceObj) External (PCI0.LPCB, DeviceObj) [...] Scope (PCI0.LPCB) { Device (TPM) [...] Scope (\_SB.PCI0.GFX0) { Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices [...] """ SSDT excerpt with the patch: """ DefinitionBlock ("", "SSDT", 2, "CORE ", "COREBOOT", 0x0000002A) { External (_SB_.PCI0.GFX0, DeviceObj) [...] External (_SB_.PCI0.LPCB, DeviceObj) [...] External (_SB_.PCI0.SATA, DeviceObj) [...] Scope (\_SB.PCI0.LPCB) { Device (TPM) [...] Scope (\_SB.PCI0.GFX0) { Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices [...] """ After the patch the TPM shows up in /sys/bus/acpi/devices/PNP0C31:00. Previously it was missing and not detected by the kernel. Change-Id: I615b4873ca829a859211403c84234d43d60f2243 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/18315 Tested-by: build bot (Jenkins) Reviewed-by: Nicola Corna <nicola@corna.info> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-26drivers/pc80/rtc: Check cmos checksum BEFORE reading cmos valueMartin Roth
If cmos is invalid, it doesn't make sense to read the value before finding that out. Change-Id: Ieb4661aad7e4d640772325c3c6b184de1947edc3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18236 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-16drivers/pc80/tpm: Set default TPM acpi path if unsetPhilipp Deppenwiese
Enable default acpi path PCI0.LPCB if TPM support is selected in the kconfig system and the acpi path is not set via acpi_name callback in the platform code. Thanks to Aaron Durbin for providing this fix. Change-Id: Idb56cafe71efc8a52eee5a5a663478da99152360 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/17855 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-13pc80: Move set_boot_successful()Kyösti Mälkki
Don't implement arch or driver -specific code under lib/, Change-Id: If75980ec5efc622582e2b5e124ad0e7ee3fa39a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17793 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-28Build system: Update HAVE_CMOS_DEFAULTMartin Roth
- Don't build the cmos.default file into cbfs if USE_OPTION_TABLE isn't specified. - Don't allow HAVE_CMOS_DEFAULT if HAVE_OPTION_TABLE isn't set. Change-Id: I92401e892f09fc95d4b3fd7418cdbd10ed033fa8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17454 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24driver/pc80/tpm: Runtime generate ACPI table for TPM driverNaresh G Solanki
Runtime write acpi table for TPM driver. Change-Id: I70896e5874c24f17fca0c48b138ad4917b273f5b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17425 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-17rtc: Force negative edge on SET after battery replacementMarshall Dawson
After the RTC coin cell has been replaced, the Update Cycle Inhibit bit must see at least one low transition to ensure the RTC counts. The reset value for this bit is undefined. Examples have been observed where batteries are installed on a manufacturing line, the bit's state comes up low, but the RTC does not count. Change-Id: I05f61efdf941297fa9ec90136124b0c8fe0639c6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17370 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17rtc: Check update-in-progress bitMarshall Dawson
While the real-time clock updates its count, values may not be correctly read or written. On reads, ensure the UIP bit is clear which guarantees a minimum of 244 microseconds exists before the update begins. Writes already avoid the problem by disabling the RTC count via the SET bit. Change-Id: I39e34493113015d32582f1c280fafa9e97f43a40 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17369 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-14drivers/pc80/tpm: Select TPM device name based on Kconfig optionSubrata Banik
Device ID remains same for SLB9670 Infineon TPM 1.1 and TPM 2.0 chip. Hence select based on TPM2 Kconfig option. BUG=none BRANCH=none TEST=Build and boot SKL RVP with SPI TPM 2.0 module Change-Id: I57e63f2f2899d25ed6b797930fd8bf1d1cdc1b1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17374 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-02Kconfig: Update default hex values to start with 0xMartin Roth
Kconfig hex values don't need to be in quotes, and should start with '0x'. If the default value isn't set this way, Kconfig will add the 0x to the start, and the entry can be added unnecessarily to the defconfig since it's "different" than what was set by the default. A check for this has been added to the Kconfig lint tool. Change-Id: I86f37340682771700011b6285e4b4af41b7e9968 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16834 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-21Makefiles: update cbfs types from bare numbers to valuesMartin Roth
These values are found in util/cbfstool/cbfs.h. Change-Id: Iea4807b272c0309ac3283e5a3f5e135da6c5eb66 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16646 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-31src/drivers: Capitalize CPU, RAM and ACPIElyes HAOUAS
Change-Id: I720469ea1df75544f5b1e0cab718502d8a9cf197 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15983 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-06rtc: Do checksum check for all bytesStefan Reinauer
Due to missing braces (that went undetected because of the indentation), I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8 CMOS: add set_option() only takes the last changed byte into regard when determining whether the checksum needs to be updated. This bug went undetected for 5 years. Change-Id: I47cedc801a60959386dfdcda3a13b8e3162a7ecb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14616 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Also, fix up the following driver subdirectories by switching to the src/drivers/[X]/[Y]/ scheme as these are hard requirements for the main change: * drivers/intel * drivers/pc80 * drivers/dec Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14047 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i440BX boards in the chipset. Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13781 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-05tpm/acpi/tpm.asl: Only include tpm.asl if tpm is enabledMartin Roth
If the TPM code isn't getting built in, the Kconfig symbol CONFIG_TPM_TIS_BASE_ADDRESS doesn't exist. This ends up creating an invalid operating region in the ACPI tables, causing a bluescreen in windows. This should fix this issue: https://ticket.coreboot.org/issues/35 "commit 85a255fb (acpi/tpm: Gracefully handle missing TPM module) breaks Windows" Change-Id: I32e0e09c1f61551a40f4842168f556d5e1940d28 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13890 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
Change-Id: Ib73abb0ada7dfdfab3487c005719e19f51ef1812 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/13779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-18acpi/tpm: Gracefully handle missing TPM module.Tobias Diedrich
When TPM support is enabled, verify the TPM_DID_VID field is not all zeroes or all ones before returning 0xf in the _STA method. This avoids these kernel errors when no module is installed: [ 3.426426] tpm_tis 00:01: tpm_transmit: tpm_send: error -5 [ 3.432049] tpm_tis: probe of 00:01 failed with error -5 Change-Id: Ia089d4232e0986b3bc635d346e68d982e8aecd44 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/13713 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-02-01drivers/pc80: Add PS/2 mouse presence detectTimothy Pearson
On certain Winbond SuperIO devices, when a PS/2 mouse is not present on the auxiliary channel both channels will cease to function if the auxiliary channel is probed while the primary channel is active. Therefore, knowledge of mouse presence must be gathered by coreboot during early boot, and used to enable or disable the auxiliary PS/2 port before control is passed to the operating system. Add auxiliary channel PS/2 device presence detect, and update the Winbond W83667HG-A driver to flag the auxiliary channel as disabled if no device was detected. Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13165 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-18drivers/pc80: Add optional spinlock for nvram CBFS accessTimothy Pearson
When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following: AMD-Vi: Event logged [IO_PAGE_FAULT device=00:14.0 domain=0x000a address=0x000000fdf9103300 flags=0x0030] Decoding the faulting address: 0x000000fdf9103300 fdf91x Hypertransport system management region 33 SysMgtCmd (System Management Command) = 0x33 3 Base Command Type = 0x3: STPCLK (Stop Clock request) 3 SMAF (System Management Action Field) = [3:1] = 0x1 1 Signal State Bit Map = [0] = 0x1 Therefore, the error appears to be triggered by an upstream C1E request. This was eventually traced to concurrent access to the SP5100's SPI Flash controller by multiple APs during startup. Calls to the nvram read functions get_option and read_option call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash controller, thus placing the SP5100 in an invalid state. This limitation is not documented in any public AMD errata, and was only discovered through considerable debugging effort. Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12061 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-06Remove #ifdef checks on Kconfig symbolsMartin Roth
In coreboot, bool, hex, and int type symbols are ALWAYS defined. Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12560 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-03drivers/pc80: Rework normal / fallback selector codeTimothy Pearson
Per IRC and Gerrit discussion, the normal / fallback selector code is a rather weak spot in coreboot, and did not function correctly for certain use cases. Rework the selector to more clearly indicate proper operation, and also remove dead code. Also tentatively abandon use of RTC bit 385; a follow-up patch will remove said bit from all affected mainboards. The correct operation of the fallback code selector approximates that of a power line recloser, with a user option to attempt normal boot that can be cleared by firmware, but never set by firmware. Additionally, if cleared by user, the fallback path should always be used on the next reboot. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12289 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-27tpm: acpi: Add support for TPM PIRQDuncan Laurie
With SPI TPMs there is no SERIRQ for interrupts, instead it is a PIRQ based interrupt. The TCG PC Client Platform TPM Profile Specification says it must be active low and shared. This can be enabled with the CONFIG_TPM_PIRQ option that will specify the interrupt vector to report for the TPM. BUG=chrome-os-partner:40635 BRANCH=none TEST=verify TPM interrupt functionality in /proc/interrupts on glados Change-Id: Iad3ced213d1fc5380c559f50c086206dc9f22534 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: abdd0b8ecdf51ff32ed8bfee0823bbc30d5d3d49 Original-Change-Id: If7d22dfcfcab95dbd4c9edbd8674fc8d948a62d2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/304133 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12147 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-14x86: add standalone verstage supportAaron Durbin
To support x86 verstage one needs a working buffer for vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage. Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-28tpm: acpi: Make _CRS method serializedDuncan Laurie
Since the TPM _CRS method creates named objects it needs to be serialized to prevent a warning in recent iasl. BUG=chrome-os-partner:40635 BRANCH=none TEST=build glados with iasl-20150717 Change-Id: I59a52552ab24b7d9c9928331aa8c8d19f54fd1b7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2a5c474c94980661573a99eb94d5f661f2d0114b Original-Change-Id: Ie9d164ea8781304dd0bf1833d182d7c601b8e18d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302162 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11715 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-09drivers/pc80: Do not initialize PS2 keyboard by defaultAlexandru Gagniuc
The most common payloads do not need this set, so optimize for the common case. Change-Id: I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8599 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-09-08drivers/pc80/tpm: Set "Found TPM" message to BIOS_INFO levelDuncan Laurie
Having no supplied printk level makes this info message printed at all levels and so it shows up when booting with DEFAULT_CONSOLE_LOGLEVEL=3. BUG=chrome-os-partner:40635 BRANCH=none TEST="USE=quiet-cb emerge-glados coreboot" Change-Id: I6c52aafbe47fdf297e2caeb05b4d79a40a9a4b9d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e6cffc6d5a9fcda60a04f8a31f2b2ffe4b620c77 Original-Change-Id: Ie6715d15f950d184805149619bebe328d528e55a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297336 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11559 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-09drivers/pc80/i8254.c: Indent with GNU indent 2.2.11Paul Menzel
Run `indent -linux src/drivers/pc80/i8254.c` and manually put the `;` in the while loop back on a separate line. Change-Id: I58c4c5df3846a91ef92aafb608962dc26a21f811 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10452 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-07Fix Kconfig whitespace.Martin Roth
All other Kconfig locations start with tabs. Change-Id: I0ee5f0b0b82f85c8ae58b3626f142f159554efb3 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10438 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-02tpm: Add dummy _DSM to make Bitlocker happy.Vladimir Serbinenko
Change-Id: Ieb6f70f5b2863336bd6143b2dfbb1d67c4c26109 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10323 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02cbfs: new API and better program loadingAaron Durbin
A new CBFS API is introduced to allow making CBFS access easier for providing multiple CBFS sources. That is achieved by decoupling the cbfs source from a CBFS file. A CBFS source is described by a descriptor. It contains the necessary properties for walking a CBFS to locate a file. The CBFS file is then decoupled from the CBFS descriptor in that it's no longer needed to access the contents of the file. All of this is accomplished using the regions infrastructure by repsenting CBFS sources and files as region_devices. Because region_devices can be chained together forming subregions this allows one to decouple a CBFS source from a file. This also allows one to provide CBFS files that came from other sources for payload and/or stage loading. The program loading takes advantage of those very properties by allowing multiple sources for locating a program. Because of this we can reduce the overhead of loading programs because it's all done in the common code paths. Only locating the program is per source. Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9134 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02TPM: Add Infineon SLB9670 SPI TPM supportWenkai Du
This patch provides support for TPM Infineon SLB9670 by adding its device ID to the list. BRANCH=None BUG=chrome-os-partner:40640 TEST=Built and test SLB9670 on SKL U Reference board Fab 2 Change-Id: I2d26fc6c7d074881f2e6189e1325808544b7d26d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c92884be75b631c302801e162292c245ed7bf5d Original-Change-Id: I4607fc96f70175b2461b40ba61e7a821e187de40 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/274053 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-29tpm: Add Infineon TPM 1.2 supportSubrata
This patch provides support for TPM Infineon TT1.2 devices by enumerating the TT1.2 ID in the Infineon device list. BRANCH=None BUG=None TEST=Built for sklrvp and tested on RVP3. Change-Id: I9daecc09311477fd9947e829d80abc040b2c9e3d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3ff86f96cb3e2f203dbc86e7004f1a037b98b90a Original-Change-Id: I8b59eba348fc44632e22600646eb0b10eb2f4901 Original-Signed-off-by: Subrata <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271256 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/10302 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-29tpm: Fix multiple device supportSubrata
Current TPM driver does not support multiple devices for a given vendor. As the device object never takes the 2nd ID in the list. This patch fixes the same. BRANCH=None BUG=None TEST=Built for sklrvp and tested on RVP3. Change-Id: I82c3267c6c74b22650fc53dc6abdc2eb3daa138e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ff42613f11b4f1a79e907601f1ecb7b83a3aeaab Original-Change-Id: Ieb44735c37208bfe90a8e22e0348dd41c8c642d2 Original-Signed-off-by: Subrata <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271727 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Commit-Queue: Pravin K Angolkar <pravin.k.angolkar@intel.com> Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com> Reviewed-on: http://review.coreboot.org/10303 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-27Deactivate TPMVladimir Serbinenko
Just not exporting TPM isn't good enough as it can still be accessed. You need to send it a deactivate command. Change-Id: I3eb84660949c2d1e2b492d541e01d4ba78037630 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10270 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-27Move TPM code out of chromeosVladimir Serbinenko
This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10269 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-23Hide TPM_TIS_BASE_ADDRESSVladimir Serbinenko
TPM_TIS_BASE_ADDRESS is technical setting, shouldn't be user-visible. Change-Id: Ibf74f52be16fb7d2cfa78419087a4c3e7607368a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10271 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-07kbuild: Use wildcard for driver subdirectoriesStefan Reinauer
Change-Id: Id1685c0b28ec8e3ab972a671af6f2de6f321c645 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9805 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22rtc: add config flag to denote rtc API availabilityPatrick Georgi
RTC drivers now select RTC, so that code which depends on them can implement fallback behavior for systems that lack the hardware or driver. Change-Id: I0f5a15d643b0c45c511f1151a98e071b4155fb5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9953 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-21Unify byte order macros and clrsetbitsJulius Werner
This patch removes quite a bit of code duplication between cpu_to_le32() and clrsetbits_le32() style macros on the different architectures. This also syncs those macros back up to the new write32(a, v) style IO accessor macros that are now used on ARM and ARM64. CQ-DEPEND=CL:254862 BRANCH=none BUG=chromium:444723 TEST=Compiled Cosmos, Daisy, Blaze, Falco, Pinky, Pit, Rambi, Ryu, Storm and Urara. Booted on Jerry. Tried to compare binary images... unfortunately something about the new macro notation makes the compiler evaluate it more efficiently (not recalculating the address between the read and the write), so this was of limited value. Change-Id: If8ab62912c952d68a67a0f71e82b038732cd1317 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fd43bf446581bfb84bec4f2ebb56b5de95971c3b Original-Change-Id: I7d301b5bb5ac0db7f5ff39e3adc2b28a1f402a72 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254866 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Manually clean up the mess left by write32() transitionJulius Werner
This patch is a manual cleanup of all the rubble left by coccinelle waltzing through our code base. It's generally not very good with line breaks and sometimes even eats comments, so this patch is my best attempt at putting it all back together. Also finally remove those hated writel()-style macros from the headers. BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: Id572f69c420c35577701feb154faa5aaf79cd13e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 817402a80ab77083728b55aed74b3b4202ba7f1d Original-Change-Id: I3b0dcd6fe09fc4e3b83ee491625d6dced98e3047 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254865 Reviewed-on: http://review.coreboot.org/9837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Globally replace writel(v, a) with write32(a, v)Julius Werner
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-13tpm: Only expose base address Kconfig option when enabledPatrick Georgi
Change-Id: Ia8ddd689a3bf09ed68f94907ea19d4d2ee874542 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/9594 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tpm: Remove error message for unknown resource typeDuncan Laurie
This is being triggered because the base address is added, but there is nothing that needs done with it in set_resources step and the ERROR message is tripping suspend resume test scripts. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=boot on samus and check for ERROR strings, successfully run suspend_stress_test without failures Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/231603 (cherry picked from commit bb789492965d92e309a913dc7b9f09f7036c5480) Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I565c8af954f1c5a406d2c65f01c274e9259e43ec Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9062734d884f814dc880589ee615b4d7e1fdc61a Original-Change-Id: I2b5f44795f1ee445d509b29bd56f498aea7b7fe3 Original-Reviewed-on: https://chromium-review.googlesource.com/231604 Original-Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9476 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Add ramstage driver and interrupt configurationDuncan Laurie
This adds a ramstage driver for the TPM and allows the interrupt to be configured in devicetree.cb. The interrupt vector is set like other PNP devices, and the interrupt polarity is set with a register configuration variable. These values are written into locality 0 TPM_INT_VECTOR and TPM_INT_ENABLE and then all interrupts are disabled so they are not used in firmware but can be enabled by the OS. It also adds an ACPI device for the TPM which will configure the reported interrupt based on what has been written into the TPM during ramstage. The _STA method returns enabled if CONFIG_LPC_TPM is enabled, and the _CRS method will only report an interrupt if one has been set in the TPM itself. The TPM memory address is added by the driver and declared in the ACPI code. In order to access it in ACPI a Kconfig entry is added for the default TPM TIS 1.2 base address. Note that IO address 0x2e is required to be declared in ACPI for the kernel driver to probe correctly. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=manual testing on samus: 1) Add TPM device in devicetree.cb with configured interrupt and ensure that it is functional in the OS. 2) Test with active high and active low, edge triggered and level triggered setups. 3) Ensure that with no device added to devicetree.cb that the TPM is still functional in polling mode. Change-Id: Iee2a1832394dfe32f3ea3700753b8ecc443c7fbf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fc2c106caae939467fb07f3a0207adee71dda48e Original-Change-Id: Id8a5a251f193c71ab2209f85fb470120a3b6a80d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226661 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9469 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 00:45:49 +0000