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2022-03-18Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run ↵Nick Vaccaro
serially"" This reverts a change that was causing hangs and exceptions during boot on an ADL brya4es. The hang (or APIC exception) occurs at what appears to be the FSP MP initialization sequence, prior to the "Display FSP Version Info HOB" log being displayed : [DEBUG] Detected 10 core, 12 thread CPU. [DEBUG] Display FSP Version Info HOB This reverts commit 40ca79714ad7d5f2aa201d83db4d97f21260d924. BUG=b:224873032 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and verify brya4es is able to successfully reboot 200 times without any issues. Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially"Ronak Kanabar
This reverts commit 6af980a2aeca9b8cedfb3d7734389e6e36099c88. BUG=b:199246420 Change-Id: Iddb7aa6d52b563485a496798f2fe31ed64b4f4a8 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-03-08timestamps: Rename timestamps to make names more consistentJakub Czapiga
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-21drivers/intel/fsp2_0/hob: Remove unused variableArthur Heymans
Change-Id: Ie9f4562be9b019d8dd65d4e9040fefbb6834fa03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-18drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik
This patch renames all FSP Notify Phase API configs to primarily remove "SKIP_" prefix. 1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM -> USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT -> USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -> USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE The idea here is to let SoC selects all required FSP configs to execute FSP Notify Phase APIs unless SoC deselects those configs to run native coreboot implementation as part of the `.final` ops. For now all SoC that uses FSP APIs have selected all required configs to let FSP to execute Notify Phase APIs. Note: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. Additionally, fixed SoC configs inclusion order alphabetically.  BUG=b:211954778 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-16drivers/intel/fsp: Set FSP_LOG_LEVEL_ERR_WARN_INFO for DEBUG_RAM_SETUPKane Chen
To get verbose MRC log includes RMT log, we need to set FSP_LOG_LEVEL_ERR_WARN_INFO instead. TEST=tested on gimble, see MRC verbose and RMT log are printed Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Change-Id: I3896f0482dfde090b4e087490b7937683b5de091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-02drivers/intel/fsp2_0/include/fsp: fix fsp_headerJulian Schroeder
This patch aligns fsp_header with the Intel specification 2.0 and 2.3. The main impetus for this change is to make the fsp_info_header fully accessible in soc/vendor code. Here items such as image_revision can be checked. TEST=verify image revision output in the coreboot serial log. compare to FSP version shown in serial debug output. verify Google Guybrush machine boots into OS. Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: Ibf50f16b5e9793d946a95970fcdabc4c07289646 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-25drivers/intel/fsp2_0: Make FSP Notify Phase APIs optionalSubrata Banik
The FSP API is used to notify the FSP about different phases in the boot process. The current FSP specification supports three notify phases: - Post PCI enumeration - Ready to Boot - End of Firmware This patch attempts to make calling into the FSP Notify Phase APIs optional by using native coreboot implementations to perform the required lock down and chipset register configuration prior boot to payload. BUG=b:211954778 TEST=Able to build brya without any compilation issue and coreboot log with this code changes when SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT and SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config enabled. coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia95e9ec25ae797f2ac8e1c74145cf21e59867d64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-17drivers/intel/fsp2_0: Add FSP 2.3 supportAnil Kumar
FSP 2.3 specification introduces following changes: 1. FSP_INFO_HEADER changes Updated SpecVersion from 0x22 to 0x23 Updated HeaderRevision from 5 to 6 Added ExtendedImageRevision FSP_INFO_HEADER length changed to 0x50 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 Following changes are implemented in the patch to support FSP 2.3: - Add Kconfig option - Update FSP build binary version info based on ExtendedImageRevision field in header - New NV HOB related changes will be pushed as part of another patch Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-03drivers/intel/fsp: Map FSP debug level to coreboot console levelSubrata Banik
This patch maps coreboot console level to FSP debug level. This is useful to suppress MRC (FSP-M) debug logs. Callers have to select HAVE_DEBUG_RAM_SETUP config to get verbose MRC debug log, Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I398d576fad68a0d0fc931c175bbc04fcbc2e54ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-02drivers/intel/fsp2_0/notify.c: Group per-phase dataAngel Pons
Group all data specific to each notify phase in a struct to avoid redundant code. Change-Id: Ib4ab3d87edfcd5426ce35c168cbb780ade87290e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-02drivers/intel/fsp2_0/notify.c: Clean up some cosmeticsAngel Pons
Sort includes alphabetically, drop spaces after type casts and unbreak some long lines that are less than 96 characters long. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I2dafd677abbdd892745fea1bf4414f6e0d5549bb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-02drivers/intel/fsp2_0: Print return value when dyingAngel Pons
When coreboot goes to die because FSP returned an error, log the return value in the message printed by `die()` or `die_with_post_code()`. Change-Id: I6b9ea60534a20429f15132007c1f5770760481af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2021-11-08drivers/intel/fsp2_0: Add preload_fspm and preload_fspsRaul E Rangel
In the non-XIP world, FSP is normally memmapped and then decompressed. The AMD SPI DMA controller can actually read faster than mmap. So by reading the contents into a buffer and then decompressing we reduce boot time. BUG=b:179699789 TEST=Boot guybrush and see 30ms reduction in boot time Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-08drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X optionRaul E Rangel
This option will allow setting the FSP alignment in CBFS. BUG=b:179699789 TEST=Boot with and without the option set and verify -a option was passed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-08drivers/intel/fsp2_0: Allow FSP-M to be relocatedRaul E Rangel
AMD platforms pass in the base address to cbfs tool: fspm.bin-options: -b $(CONFIG_FSP_M_ADDR) There is no technical reason not to allow FSP-M to be relocated when !XIP. By allowing this, we no longer need to pass in the base address into cbfstool when adding fspm.bin. This enables passing in the `--alignment` argument to cbfs tool instead. cbfstool currently has a check that prevents both `-b` and `-a` from being passed in. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-30drivers/intel/fsp2_0: Check return type against CB_SUCCESSSubrata Banik
commit 6af980a2a (drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially) drops CB_SUCCESS check for mp_run_on_all_aps function hence, this changes bring back the required return type against CB_SUCCESS. Change-Id: I9fc81e6a7eebbf0072ea2acb36b3c33539b517a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run seriallySubrata Banik
As per MP service specification, EDK2 is allowed to specify the mode in which a 'func' routine should be executed on APs. `SingleThread` sets to 'true' meaning to execute the function one by one (serially) or sets to 'false' meaning to execute the function simultaneously. MP service API `StartupAllAPs` was designed to pass such options as part of function argument. But another MP service API `StartupAllCPUs` doesn't specify any such requirement. Running the `func` simultaneously on APs results in a coherency issue (hang while executing `func`) due to lack of acquiring a spin lock while accessing common data structure in multiprocessor environment. BUG=b:199246420 Change-Id: Ia95d11408f663212fd40daa9fd9b0881a07f1ce7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-22cpu/x86/mp_init: use cb_err as status return type in remaining functionsFelix Held
Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps, mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of all 4 functions listed above against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-05drivers/intel/fsp2_0: don't force-use `python2`Michael Niewöhner
Some distributions (e.g. NixOS, Debian) are actively working on getting rid of EOL Python 2. Since `SplitFspBin.py` supports both Python 2 and Python 3 as of upstream commit 0bc2b07, use whatever version is present by utilizing `python`. Change-Id: I2a657d0d4fc1899266a9574cfdfec1380828d72d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-16drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling methodSubrata Banik
FspMultiPhaseSiInit API was introduced with FSP 2.2 specification onwards. EnableMultiPhaseSiliconInit is an arch UPD also introduced as part of FSP 2.2 specification to allow calling FspMultiPhaseSiInit API. However, some platforms adhere to the FSP specification but don't have arch UPD structure, for example : JSL, TGL and Xeon-SP. Out of these platforms, TGL supports calling of FspMultiPhaseSiInit API and considered EnableMultiPhaseSiliconInit as a platform-specific UPD rather than an arch UPD to allow calling into FspMultiPhaseSiInit API. It is important to ensure that the UPD setting and the callback for MultiPhaseInit are kept in sync, else it could result in broken behavior e.g. a hang is seen in FSP if EnableMultiPhaseSiliconInit UPD is set to 1 but the FspMultiPhaseSiInit API call is skipped. This patch provides an option for users to choose to bypass calling into MultiPhaseSiInit API and ensures the EnableMultiPhaseSiliconInit UPD is set to its default state as `disable` so that FSP-S don't consider MultiPhaseSiInit API is a mandatory entry point prior to calling other FSP API entry points. List of changes: 1. Add `FSPS_HAS_ARCH_UPD` Kconfig for SoC to select if `FSPS_ARCH_UPD` structure is part of `FSPS_UPD` structure. 2. Drop `soc_fsp_multi_phase_init_is_enable()` from JSL and Xeon-SP SoCs, a SoC override to callout that SoC doesn't support calling MultiPhase Si Init is no longer required. 3. Add `FSPS_USE_MULTI_PHASE_INIT` Kconfig for SoC to specify if SoC users want to enable `EnableMultiPhaseSiliconInit` arch UPD (using `fsp_fill_common_arch_params()`) and execute FspMultiPhaseSiInit() API. 4. Presently selects `FSPS_USE_MULTI_PHASE_INIT` from IA TCSS common code. 5. Add `fsp_is_multi_phase_init_enabled()` that check applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API to honor SoC users' decision. 6. Drop `arch_silicon_init_params()` from SoC as FSP driver (FSP 2.2) would check the applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API. Additionally, selects FSPS_HAS_ARCH_UPD for Alder Lake as Alder Lake FSPS_UPD structure has `FSPS_ARCH_UPD` structure and drops `arch_silicon_init_params()` from SoC `platform_fsp_silicon_init_params_cb()`. Skip EnableMultiPhaseSiliconInit hardcoding for Tiger Lake and uses the fsp_is_multi_phase_init_enabled() function to override EnableMultiPhaseSiliconInit UPD prior calling MultiPhaseSiInit FSP API. TEST=EnableMultiPhaseSiliconInit UPD is getting set or reset based on SoC user selects FSPS_USE_MULTI_PHASE_INIT Kconfig. Change-Id: I019fa8364605f5061d56e2d80b20e1a91857c423 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16drivers/intel/fsp2_0: Pass orientation to fsp_report_framebuffer_infoTim Wawrzynczak
Instead of always passing LB_FB_ORIENTATION_NORMAL, allow the chipsets implementing the callback to pass in an orientation. BUG=b:194967458 BRANCH=dedede Change-Id: I4aacab9449930a75aca9d68bf30d019f86035405 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09drivers/intel/fsp2_0: Retype loop variable from int to uint32_tAngel Pons
Retype loop variable `i` to `uint32_t` for consistency with the types of the `number_of_phases` and `phase_index` struct fields and the parameter of the `platform_fsp_multi_phase_init_cb()` function. Change-Id: I82916f33c2dc5dab6a31111c9acba2a18a5cfb0b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57491 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06drivers/intel/fsp2_0: add warning when ADD_FSP_BINARIES isn't selectedFelix Held
Platforms that rely on the FSP for parts of the hardware initialization likely won't boot successfully when no FSP binaries are added during the build, so print a warning at the end of the build in this case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Suggested-by: Martin Roth <martinroth@google.com> Change-Id: I6efc184ecc4059818474937fd31574f703c9bdc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-05drivers/intel/fsp/Makefile: error out when FSP files aren't specifiedFelix Held
Error out when the FSP binaries that are supposed to be added aren't specified. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: Ie5f2d75d066f0b4e491e9c8420b7a0cbd4ba9e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-03drivers/intel/fsp2_0/Makefile: add condition for FSP-T CBFS fileFelix Held
Make adding the FSP-T file to CBFS depend on both ADD_FSP_BINARIES and FSP_CAR Kconfig options being set. The FSP_T_FILE Kconfig option depends on both, so also check if both are selected in the Makefile where it tries to add the FSP-T to the CBFS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Id347336f2751c6d871f31d89c30a1222037c2d69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-26drivers/intel/fsp2_0: rename soc_validate_fsp_versionFelix Held
Rename soc_validate_fsp_version to soc_validate_fspm_header, since it can not only be used to check the version info in the FSP-M binary's header, but also to check every other field in the binary's header. This is a preparation for a follow-up patch that implements this function to check the FSP-M binary's size. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Ifadcfd1869bea0774dc17b69c5d1e1c241a45de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-24src/drivers/intel/fsp2_0: allow larger FSP 2.0 headerNikolai Vyssotski
This is in preparation for migrating EDK2 to more recent version(s). In EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0 header (FspMultiPhaseSiInitEntryOffset). This increases the length of the header from 72 to 76. Instead of checking for exact length check reported header length against known minimum length for a given FSP version. BUG=b:180186886 TEST=build/boot with both header flavors Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56190 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region"Felix Held
This reverts commit ce0e2a014009390c4527e064efb59260ef4d3a3b which was originally introduced as a workaround for the bug that the Linux kernel doesn't know what to do with type 16 memory region in the e820 table where CBMEM resides and disallowed accessing it. After depthcharge was patched to mark the type 16 region as a normal reserved region, the Linux kernel now can access the BERT region and print BERT errors. When SeaBIOS was used as payload it already marked the memory region correctly, so it already worked in that case. After commit 8c3a8df1021b8a2789c2a285557401837f9fc2b8 that removed the usage of the BERT memory region reserved by the FSP driver by the AMD Picasso and Cezanne SoCs and made them use CBMEM for the BERT region, no other SoC code uses this functionality. The Intel Alderlake and Tigerlake SoCs put the BERT region in CBMEM and never used this reserved memory region and the change for the Intel server CPU to use this was abandoned and never landed in upstream coreboot. AMD Stoneyridge is the only other SoC/chipset that selects ACPI_BERT, but since it doesn't select or use the FSP driver, it also won't be affected by this change. TEST=Behavior of the BERT code doesn't change on Mandolin Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56163 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-02drivers/intel/fsp2: Change FSPS returned message to INFORaul E Rangel
This message is not an error, but just informational. BUG=none TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see it printed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifb64edbe029cafa82aec99aa50de47f51cd50dce Reviewed-on: https://review.coreboot.org/c/coreboot/+/55971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-06-18intel/fsp2_0: Add FSP_ARRAY_LOAD macroLean Sheng Tan
Add FSP_ARRAY_LOAD macro for checking and loading array type configs into array type UPDs to increase readability. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I307340a2bfc0a54f2ab7241af2f24dfbf8bb111d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55559 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPSMartin Roth
The loads of the FSPM and FSPS binaries are not insignificant amounts of time, and without these timestamps, it's not clear what's going on in those time blocks. For FSPM, the timestamps can run together to make it look like that time is still part of the romstage init time. Example: 6:end of verified boot 387,390 (5,402) 13:starting to load romstage 401,931 (14,541) 14:finished loading romstage 420,560 (18,629) 970:loading FSP-M 450,698 (30,138) 15:starting LZMA decompress (ignore for x86) 464,173 (13,475) 16:finished LZMA decompress (ignore for x86) 517,860 (53,687) ... 9:finished loading ramstage 737,191 (18,377) 10:start of ramstage 757,584 (20,393) 30:device enumeration 790,382 (32,798) 971:loading FSP-S 840,186 (49,804) 15:starting LZMA decompress (ignore for x86) 853,834 (13,648) 16:finished LZMA decompress (ignore for x86) 888,830 (34,996) BUG=b:188981986 TEST=Build & Boot guybrush, look at timestamps. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5796d4cdd512799c2eafee45a8ef561de5258b91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-29drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function staticSubrata Banik
fsp_temp_ram_exit() function is only getting called by late_car_teardown() function inside temp_ram_exit.c file. Hence, make function as static and removed from include/fsp/api.h. Change-Id: I2239400e475482bc21f771d41a5ac524222d40fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-12include/console: Fix FSP Notify phase postcodes discrepancySubrata Banik
List of changes: 1. Make the FSP notify phases name prior in comments section. 2. Fix discrepancies in FSP notify before and after postcode comments. 3. Add FSP notify postcode macros for after pci enumeration(0xa2) and ready to boot(0xa3) call. Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52894 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05drivers/intel/fsp2_0: Fix the FSP-T positionArthur Heymans
The only use case for FSP-T in coreboot is for 'Intel Bootguard' support at the moment. Bootguard can do verification FSP-T but there is no verification on whether the FSP found by walkcbfs_asm is the one actually verified as an IBB by Bootguard. A fixed pointer needs to be used. TESTED on OCP/Deltalake, still boots. Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-16drivers/intel/fsp2_0: Add support to identify GPIO config changesFurquan Shaikh
Traditionally, for each Intel platform using FSP, FSP-S has at some point configured GPIOs differently than the mainboard configuration in coreboot. This has resulted in various side-effects in coreboot, payload and OS because of misconfigured GPIOs. On more recent Intel platforms, a UPD `GpioOverride` is added that coreboot can use to ensure that FSP does not touch any GPIO configuration. This change adds a debug option `CHECK_GPIO_CONFIG_CHANGES` to fsp2_0 driver in coreboot that makes a platform callback `gpio_snapshot` to snapshot GPIO configuration before making a call to FSP SiliconInit and Notify phases. This snapshot is then compared against the GPIO configuration using platform callback `gpio_verify_snapshot` after returning from FSP. The callbacks are not added to romstage (FSP-M) because mainboard configures all pads in ramstage. This debug hook allows developers to dump information about any pads that have a different configuration after call to FSP in ramstage. It is useful to identify missed UPD configurations or bugs in FSP that might not honor the UPDs set by coreboot. This debug hook expects the platform to implement the callbacks `gpio_snapshot` and `gpio_verify_snapshot`. These can be implemented as part of the common GPIO driver for platforms using FSP2.0+. Platforms that implement this support must select the config `HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT` to make the debug config `CHECK_GPIO_CONFIG_CHANGES` visible to user. Proposal for the GPIO snapshot/verify support was discussed in the RFC CB:50829. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I5326fc98b6eba0f8ba946842253b288c0d42c523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50989 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14intel: mma: Use new CBFS APIJulius Werner
This patch changes the Intel MMA driver to use the new CBFS API. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Icc11d0c2a9ec1bd7a1d6af362f849dac16375433 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-14intel: fsp2_0: Move last pieces to new CBFS APIJulius Werner
This patch ports the last remaining use of cbfs_boot_locate() in the Intel FSP drivers to the new CBFS API. As a consequence, there is no longer a reason for fsp_validate_component() to operate on rdevs, and the function is simplified to take a direct void pointer and size to a memory-mapping of the FSP blob instead. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If1f0239eefa4542e4d23f6e2e3ff19106f2e3c0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52281 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05fsp2_0: Replace fspld->get_destination() callback with CBFS allocatorJulius Werner
The Intel FSP 2.0 driver contains a custom construct that basically serves the same purpose as the new CBFS allocator concept: a callback function to customize placement of a loaded CBFS file whose size is initially unknown. This patch removes the existing implementation and replaces it with a CBFS allocator. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0b7b446a0d2af87ec337fb80ad54f2d404e69668 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-17program_loading: Replace prog_rdev() with raw start pointer and sizeJulius Werner
Since prog_locate() was eliminated, prog_rdev() only ever represents the loaded program in memory now. Using the rdev API for this is unnecessary if we know that the "device" is always just memory. This patch changes it to be represented by a simple pointer and size. Since some code still really wants this to be an rdev, introduce a prog_chain_rdev() helper to translate back to that if necessary. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If7c0f1c5698fa0c326e23c553ea0fe928b25d202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-11driver/intel/fsp2_0: Allow function to run serially on all APsAamir Bohra
EFI_PEI_MP_SERVICES_STARTUP_ALL_APS passes in a boolean flag singlethread which indicates whether the work should be scheduled in a serially on all APs or in parallel. Current implementation of this function mp_startup_all_aps always schedules work in parallel on all APs. This implementation ensures mp_startup_all_aps honors to run serialized request. BUG=b:169114674 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I4d85dd2ce9115f0186790c62c8dcc75f12412e92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51085 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.hRonak Kanabar
From JSL FSP v2376 "FirmwareVersionInfo.h" header file is added and "FirmwareVersionInfoHob.h" is deprecated. This patch adds support to display firmware version information using "FirmwareVersionInfo.h" header file. Changes included in this patch: - Add Kconfig to select FirmwareVersionInfo.h - Add code change to display firmware version info using FirmwareVersionInfo.h header No change in version info print format. BUG=b:153038236 BRANCH=None TEST=Verify JSLRVP build with all the patch in relation chain and verify the version output prints no junk data observed. couple of lines from logs are as below. Display FSP Version Info HOB Reference Code - CPU = 8.7.16.10 uCode Version = 0.0.0.1 Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-02-23intel/fsp2_0: Fix the mp_get_processor_infoAamir Bohra
FSP expects mp_get_processor_info to give processor specfic apic ID, core(zero-indexed), package(zero-indexed) and thread(zero-indexed) info. This function is run from BSP for all logical processor, With current implementation the location information returned is incorrect per logical processor. Also the processor id returned does not correspond to the processor index, rather is returned only for the BSP. BUG=b:179113790 Change-Id: Ief8677e4830a765af61a0df9621ecaa372730fca Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50880 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23drivers/intel/fsp2_0/memory_init: check if UPD struct has expected sizeFelix Held
If the UPD size in coreboot sizes mismatches the one from the FSP-M binary, we're running into trouble. If the expected size is smaller than the UPD size the FSP provides, call die(), since the target buffer isn't large enough so only the beginning of the UPD defaults from the FSP will get copied into the buffer. We ran into the issue in soc/amd/cezanne, where the UPD struct in coreboot was smaller than the one in the FSP, so the defaults didn't get completely copied. TEST=Mandolin still boots. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-17drivers/intel/fsp2_0: Allow larger FSPS UPD than expected in corebootNikolai Vyssotski
Enforcing the exact match of FSPS UPD block size between FSP and coreboot mandates simultaneous updates to coreboot and FSP repos. Allow coreboot to proceed if its UPD structure is smaller than FSP one. This usually indicates that FSPS has an updated (larger) UPD structure which should be soon matched/updated on the coreboot side to keep them in sync. While this is an undesirable situation that should be corrected ASAP, it is safe from coreboot perspective. It is safe (as long as default values in FSP UPD are sane enough to boot) because FSPS UPD buffer is allocated on the heap with the size specified in FSPS (larger) and filled with FSPS default values. This allows FSP UPD changes to be submitted first followed by changes in coreboot repo. Note that this only applies to the case when entire FSPS UPD structure grows which should be rare as FSP should allocate enough reserve space, anticipating future expansion, to keep the structure from growing when new members are added. BUG=b:171234996 BRANCH=Zork TEST=build Trembyle Change-Id: I557fd3a1f208b5b444ccf76e1552e74ecf4decad Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-09soc/amd,intel: Drop s3_resume parameter on FSP-S functionsKyösti Mälkki
ACPI S3 is a global state and it is no longer needed to pass it as a parameter. Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-09drivers/intel/fsp1_1,fsp2_0: Refactor logo displayKyösti Mälkki
Hide the detail of allocation from cbmem from the FSP. Loading of a BMP logo file from CBFS is not tied to FSP version and we do not need two copies of the code, move it under lib/. Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07src: Remove redundant <commonlib/bsd/compiler.h>Elyes HAOUAS
Change-Id: Icb3108a281dfb3f21248a7065821b8237143be1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06drivers/intel/fsp2_0: Add support for MP services2 PPIAamir Bohra
Add support for MP services2 PPIs, which is slight modification over MP services 1 PPIs. A new API StartupAllCPUs have been added to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES parameter has been removed from all MP PPI APIs. This implementation also selects the respective MP services PPI version supported for SoCs BUG=b:169196864 Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-06intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPIFurquan Shaikh
This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI in preparation to allow V1 and V2 versions of MP services PPI. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50275 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06intel: Drop FSP_PEIM_TO_PEIM_INTERFACEFurquan Shaikh
This change drops the config FSP_PEIM_TO_PEIM_INTERFACE. FSP_PEIM_TO_PEIM_INTERFACE is used for: * Auto-selecting FSP_USES_MP_SERVICES_PPI * Including src/drivers/intel/fsp2_0/ppi/Kconfig * Adding ppi to subdirs-y * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y and is selected by SoCs that want to enable MP PPI services. Instead of using the indirect path of selecting MP PPI services, this change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The above uses are handled as follows: * Auto-selecting FSP_USES_MP_SERVICES_PPI --> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI. * Including src/drivers/intel/fsp2_0/ppi/Kconfig --> The guard isn't really required. The Kconfig options in this file don't present user prompts and don't really need to be guarded. * Adding ppi to subdirs-y --> Makefile under ppi/ already has conditional inclusion of files and does not require a top-level conditional. * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y --> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04drivers/intel/fsp2_0: Fix running on x86_64Patrick Rudolph
Add new Kconfig symbols to mark FSP binary as x86_32. Fix the FSP headers and replace void pointers by fixed sized integers depending on the used mode to compile the FSP. This issue has been reported here: https://github.com/intel/FSP/issues/59 This is necessary to run on x86_64, as pointers have different size. Add preprocessor error to warn that x86_64 FSP isn't supported by the current code. Tested on Intel Skylake. FSP-M no longer returns the error "Invalid Parameter". Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01drivers/intel/fsp2_0: Use CBFS_MCACHE when coreboot tears down CARArthur Heymans
TESTED on ocp/tiogapass. Change-Id: I30560149eeaec62af4c8a982815618be5546531c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01drivers/intel/fsp2_0: Use coreboot postcar with FSP-TArthur Heymans
Allow platforms to use the coreboot postcar code instead of calling into FSP-M TempRamExit API. There are several reasons to do this: - Tearing down CAR is easy. - Allows having control over MTRR's and caching in general. - The MTRR's set up in postcar be it by coreboot or FSP-M are overwritten later on during CPU init so it does not matter. - Avoids having to find a CBFS file before cbmem is up (this causes problems with cbfs_mcache) Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48466 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30drivers/intel/fsp2_0: factor out and improve UPD signature checkFelix Held
In case of a mismatch print both the UPD signature in the FSP and the expected signature and then calls die(), since it shouldn't try calling into the wrong FSP binary for the platform. Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I469836e09db6024ecb448a5261439c66d8e65daf Reviewed-on: https://review.coreboot.org/c/coreboot/+/50090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-29stage_cache: Add resume_from_stage_cache()Kyösti Mälkki
Factor out the condition when an attempt to load stage from cache can be tried. Change-Id: I936f07bed6fc82f46118d217f1fd233e2e041405 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25drivers/intel/fsp2_0/header_display.c: Correct component_attribute checkBenjamin Doron
According to FSP_INFO_HEADER structure in FSP EAS v2.0-v2.2, BIT1 indicates an "official" build. Change-Id: I94df6050a1ad756bbeff60cda0ebac76ae5f8249 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-24arch/x86/car.ld: Account for FSP-T reserved areaArthur Heymans
Tested - on ocp/deltalake: boots (with FSP-T). - qemu/i440fx: BUILD_TIMELESS=1 results in the same binary. Change-Id: I7e364ab039b65766eb95538db6b3507bbfbfb487 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-23drivers/intel/fsp2_0: Add meaningful ERROR messageSubrata Banik
Add the "ERROR:" tag so that it ease debug effect. TEST=Test tools like "suspend_stress_test" (specific to Chrome OS) can identify the obvious coreboot ERROR prior running S3 resume test. Change-Id: I64717ce0412d43697f42ea2122b932037d28dd48 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49798 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21drivers/intel/fsp2_0: recreate FSP targets on config changeMichael Niewöhner
When a different FSP binary was chosen in menuconfig, the split fd files do not get updated. Thus, make them depend on `.config` to trigger a rebuild when the config changes. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I54739eae50fa1a47bf8f3fe2e79334bc7f7ac3d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-14drivers: Replace multiple fill_lb_framebuffer with single instancePatrick Rudolph
Currently it's not possible to add multiple graphics drivers into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics drivers can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel+Aspeed on server platforms or Intel+Nvidia on consumer notebooks. The goal is to remove duplicated fill_fb_framebuffer(), the advertisment of multiple independent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Replace all duplications of fill_fb_framebuffer and provide a single one in edid_fill_fb.c. Should not change the current behaviour as still only one graphic driver can be active at time. Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39003 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05drivers/intel/fsp2_0/memory_init: Wrap calls into FSPPatrick Rudolph
Use a wrapper code that does nothing on x86_32, but drops to protected mode to call into FSP when running on x86_64. Tested on Intel Skylake when running in long mode. Successfully run the FSP-M which is compiled for x86_32 and then continued booting in long mode. Change-Id: I9fb37019fb0d04f74d00733ce2e365f484d97d66 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48202 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04drivers/intel/fsp2_0: FSP-T requires NO_CBFS_MCACHEArthur Heymans
When FSP-T is used, the first thing done in postcar is to call FSP-M to tear down CAR. This is done before cbmem is initialized, which means CBFS_MCACHE is not accessible, which results in FSP-M not being found, failing the boot. TESTED: ocp/deltalake boots again. Change-Id: Icb41b802c636d42b0ebeb3e3850551813accda91 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48282 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01drivers/intel/fsp2_0/notify: Fix compilation under x86_64Patrick Rudolph
Change-Id: Id63b9b372bf23e80e25b7dbef09d1b8bfa9be069 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-30drivers/intel/fsp2_0: Remove console in weak functionArthur Heymans
This pollutes the log on all platforms not implementing an override. Change-Id: I0d8371447ee7820cd8e86e9d3d5e70fcf4f91e34 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48128 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-26drivers/intel/fsp2_0: move the FSP FD PATH option down in menuconfigMichael Niewöhner
Move the FSP FD PATH option down, so it gets shown in place of the split FD files, when the users chooses to use a full FD binary. Change-Id: Ie03a418fab30a908d020abf94becbaedf54fbb99 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-26drivers/intel/fsp2_0: introduce possibility of using a full FD binaryMichael Niewöhner
Currently, setting a custom FSP binary is only possible by using split FSP-T/M/S FD files. This change introduces the possibility to pass a combined FD file (the "standard" FSP format). This is done by adding a new boolean Kconfig FSP_FULL_FD, specifying that the FSP is a single FD file instead of split FSP-T/M/S FD files, and making FSP_FD_PATH user-visible when the option is chosen. In this case, the other options for split files get hidden. When the user chooses to use a full FD file instead of the split ones, the FD file gets split during build, just like it is done when selecting the Github FSP repo (FSP_USE_REPO). Test: Supermicro X11SSM-F builds and boots fine with custom FSP FD set. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I1cb98c1ff319823a2a8a95444c9b4f3d96162a02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20intel/fsp2_0: Add soc_validate_fsp_version for FSP version checkJohnny Lin
Only need to check this once so check it at romstage where the console is usually ready. Also define union fsp_revision to avoid code duplication. Change-Id: I628014e05bd567462f50af2633fbf48f3dc412bc Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-13mrc_cache: Move code for triggering memory training into mrc_cacheShelley Chen
Currently the decision of whether or not to use mrc_cache in recovery mode is made within the individual platforms' drivers (ie: fsp2.0, fsp1.1, etc.). As this is not platform specific, but uses common vboot infrastructure, the code can be unified and moved into mrc_cache. The conditions are as follows: 1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain switch is true) 2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this means that memory training will occur after verified boot, meaning that mrc_cache will be filled with data from executing RW code. So in this case, we never want to use the training data in the mrc_cache for recovery mode. 3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens before verfied boot, meaning that the mrc_cache data is generated by RO code, so it is safe to use for a recovery boot. 4. Any platform that does not use vboot should be unaffected. Additionally, we have removed the MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the mrc_cache driver takes care of invalidating the mrc_cache data for normal mode. If the platform: 1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data 2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set BUG=b:150502246 BRANCH=None TEST=1. run dut-control power_state:rec_force_mrc twice on lazor ensure that memory retraining happens both times run dut-control power_state:rec twice on lazor ensure that memory retraining happens only first time 2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig boot twice to ensure caching of memory training occurred on each boot. Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02soc/intel/common: Create common Intel FSP reset code blockSubrata Banik
Create SOC_INTEL_COMMON_FSP_RESET Kconfig to have IA common code block to handle platform reset request raised by FSP. The FSP will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that a reset is required. Make FSP_STATUS_GLOBAL_RESET depends on SOC_INTEL_COMMON_FSP_RESET. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I934b41affed7bb146f53ff6a4654fdbc6626101b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02drivers/intel/fsp2_0: Add function to report FSP-T outputArthur Heymans
This allows to compare the FSP-T output in %ecx and %edx to coreboot's CAR symbols: Change-Id: I8d79f97f8c12c63ce215935353717855442a8290 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-20mrc_cache: Move mrc_cache_*_hash functions into mrc_cache driverShelley Chen
This CL would remove these calls from fsp 2.0. Platforms that select MRC_STASH_TO_CBMEM, updating the TPM NVRAM space is moved from romstage (when data stashed to CBMEM) to ramstage (when data is written back to SPI flash. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I3088ca6927c7dbc65386c13e868afa0462086937 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-20mrc_cache: Add config MRC_SAVE_HASH_IN_TPMShelley Chen
Use this config to specify whether we want to save a hash of the MRC_CACHE in the TPM NVRAM space. Replace all uses of FSP2_0_USES_TPM_MRC_HASH with MRC_SAVE_HASH_IN_TPM and remove the FSP2_0_USES_TPM_MRC_HASH config. Note that TPM1 platforms will not select MRC_SAVE_HASH_IN_TPM as none of them use FSP2.0 and have recovery MRC_CACHE. BUG=b:150502246 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ic5ffcdba27cb1f09c39c3835029c8d9cc3453af1 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19security/vboot: Rename mem_init.h to mrc_cache_hash_tpm.hShelley Chen
As ongoing work for generalizing mrc_cache to be used by all platforms, we are pulling it out from fsp 2.0 and renaming it as mrc_cache_hash_tpm.h in security/vboot. BUG=b:150502246 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I5a204bc3342a3462f177c3ed6b8443e31816091c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-02drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory regionJonathan Zhang
APEI (ACPI Platform Error Interface) defines BERT (Boot Error Record Table) memory region: * Bootloader (firmware) generates UEFI CPER (Common Platform Error Record) records, and populates BERT region. * OS parses ACPI BERT table, finds the BERT region address, inteprets the data and processes it accordingly. When CONFIG_ACPI_BERT is defined, update FSP UPD BootLoaderTolumSize, so FSP allocates memory region for it. The APEI BERT region is placed on top of CBMEM, for the size of CONFIG_ACPI_BERT_SIZE. Apart from APEI BERT region, we also have plan to add APEI HEST region which holds OS runtime hardware error record, based on firmware first hardware error handling model. HEST region will be reserved same way as BERT region. Note that CBMEM region can not be used for such purpose, the OS (bert/hest) drivers are not able to access data held in CBMEM region, as CBMEM is set as type 16 (configuration table). An option considered was to reserve the BERT region under CBMEM. However, we do not know the size of CBMEM till acpi tables are set up. On the other hand, BERT region needs to be filled up before ACPI BERT table is finalized. Change-Id: Ie72240e4c5fa01fcf937d33678c40f9ca826487a Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-21drivers/intel/fsp2_0: Add CONFIG_FSP_STATUS_GLOBAL_RESETSubrata Banik
Add CONFIG_FSP_STATUS_GLOBAL_RESET Kconfig to get correct FSP global reset type from respective SoC Kconfig. Supported value: 0x40000003-0x40000008, These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code Unsupported value: 0xFFFFFFFF Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Idc04eb3a931d2d353808d02e62bd436b363600d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-21src/drivers: Drop unneeded empty linesElyes HAOUAS
Change-Id: I202e5d285612b9bf237b588ea3c006187623fdc3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-08-24mrc_cache: Add mrc_cache fetch functions to support non-x86 platformsShelley Chen
Create two new functions to fetch mrc_cache data (replacing mrc_cache_get_current): - mrc_cache_load_current: fetches the mrc_cache data and drops it into the given buffer. This is useful for ARM platforms where the mmap operation is very expensive. - mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a given buffer. This is useful for platforms where the mmap operation is a no-op (like x86 platforms). As the name mentions, we are not freeing the memory that we allocated with the mmap, so it is the caller's responsibility to do so. Additionally, we are replacing mrc_cache_latest with mrc_cache_get_latest_slot_info, which does not check the validity of the data when retrieving the current mrc_cache slot. This allows the caller some flexibility in deciding where they want the mrc_cache data stored (either in an mmaped region or at a given address). BUG=b:150502246 BRANCH=None TEST=Testing on a nami (x86) device: reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18src: Remove unused 'include <lib.h>'Elyes HAOUAS
Change-Id: Ic09fc4ff4ee5524d89366e28d1d22900dd0c5b4d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-17drivers/intel/fsp2_0/hand_off_block: Remove dead decrementElyes HAOUAS
Value stored to 'size' is never read. Also drop unused parameter. Change-Id: If3e96ac90f06966ee408964e0748730bc237ec19 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-13drivers/intel/fsp2_0: don't select FSP_USES_CB_STACK on FSP 2.0 platformFelix Held
soc/amd/picasso selected FSP_USES_CB_STACK even though it is FSP 2.0 based, so it doesn't reuse coreboot's stack, but sets up its own stack. In contrast to all other FSP 2.0 based platforms, this stack isn't in the CAR region, since AMD Picasso doesn't support CAR and the DRAM is already available when the x86 cores are released from reset. Selecting FSP_USES_CB_STACK ended up doing the right thing, but is semantically wrong. Instead of wrongly selecting FSP_USES_CB_STACK in soc/amd/picasso we take the corresponding code path if ENV_CACHE_AS_RAM is false which is only the case for non-CAR platforms. BUG=b:155501050 TEST=Timeless build results in an identical binary for amd/mandolin, asrock/h110m-dvs and intel/coffeelake_rvp11 which cover all 3 cases here. Change-Id: Icd0ff8e17a535e2c247793b64f4b0565887183d8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-08-13drivers/intel/fsp2_0: Fill EFI_CPU_PHYSICAL_LOCATION structure informationSubrata Banik
Latest EDK2 code inside "UefiCpuPkg\Library\RegisterCpuFeaturesLib\CpuFeaturesInitialize.c" is now looking for EFI_CPU_PHYSICAL_LOCATION structure variables hence coreboot need to fill required information (package, core and thread count). TEST=Able to see package, core and thread information as part of FSP debug log. Change-Id: Ieccf20a116d59aaafbbec3fe0adad9a48931cb59 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-08-06drivers/intel/fsp2_0: Do AP re-init after FSP-S if USE_INTEL_FSP_MP_INIT enableSubrata Banik
This patch ensures that coreboot is able to take control of APs back by doing a full AP re-initialization after FSP-S is done. TEST=Able to see all cores available after booting to OS using below command when coreboot is built with USE_INTEL_FSP_MP_INIT enable. > cat /proc/cpuinfo Without this CL : shows only 1 core (only BSP) With this CL : shows all possible cores available (BSP + APs) Change-Id: I247d8d1166c77bd01922323b6a0f14ec6640a666 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-26src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth
The Kconfig lint tool checks for cases of the code using BOOL type Kconfig options directly instead of with CONFIG() and will print out warnings about it. It gets confused by these references in comments and strings. To fix it so that it can find the real issues, just update these as we would with real issues. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove whitespace between 'sizeof' and '('Elyes HAOUAS
Change-Id: Iaf22dc1986427e8aa4521b0e9b40fafa5a29dbbd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-04lib/coreboot_table: Add Intel FSP version to coreboot tableJohnny Lin
Add a new LB_TAG_PLATFORM_BLOB_VERSION for FSP version, it would add Intel FSP version to coreboot table LB_TAG_PLATFORM_BLOB_VERSION when PLATFORM_USES_FSP2_0 is selected. Tested=On OCP Delta Lake, with an updated LinuxBoot payload cbmem utility can see "LB_TAG_PLATFORM_BLOB_VERSION": "2.1-0.0.1.120" Change-Id: I92a13ca91b9f66a7517cfd6784f3f692ff34e765 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-25drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1Jonathan Zhang
Not all FSPs based on FSP 2.1 supports the feature of external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE. Deselect FSP_PEIM_TO_PEIM_INTERFACE when PLATFORM_USES_FSP2_1 is selected. Update Kconfig of SOCs affected (icelake, jasperlake, tigerlake). Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-14drivers/intel/fsp2_0: Add FSP 2.2 specific supportSubrata Banik
• Based on FSP EAS v2.1 – Backward compatibility is retained. • Add multi-phase silicon initialization to increase the modularity of the FspSiliconInit() API. • Add FspMultiPhaseSiInit() API • FSP_INFO_HEADER changes o Added FspMultiPhaseSiInitEntryOffset • Add FSPS_ARCH_UPD o Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. FSP 2.2 Specification: https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41728 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10drivers/intel/fsp2_0: Allow SoC/mainboard to update NvsBufferPtrFurquan Shaikh
This change moves the check for NvsBufferPtr in S3 resume case to happen just before FSP-M is called. This allows SoC/mainboard code to set NvsBufferPtr if it doesn't use the default MRC cache driver. BUG=b:155990176 Change-Id: Ia272573ad7117a0cb851f0bfe6a4c7989bc64cde Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-02src: Remove redundant includesElyes HAOUAS
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>, <stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes each time when <types.h> is included. Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-28drivers/intel/fsp2_0: add option to compress FSP-M in cbfsAaron Durbin
Allow the ability for chipset or mainboard to choose to compress FSP-M in cbfs using LZMA or LZ4 routines. However, only non-XIP platforms will support FSP-M compression. Since the main cbfs decompression paths are utilized add the appropriate checks for including compression algorithms under the FSP-M compression options. On picasso FSP-M (debug builds) the following savings were measured: no-compression: fspm.bin 720896 none FSP_COMPRESS_FSP_M_LZ4: fspm.bin 138379 LZ4 (720896 decompressed) -80% FSP_COMPRESS_FSP_M_LZMA: fspm.bin 98921 LZMA (720896 decompressed) -86% BUG=b:155322763,b:150746858,b:152909132 Change-Id: I5c88510c134b56a36ff1cd97a64b51ab2fea0ab0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-28drivers/intel/fsp2_0: add option to compress FSP-S in cbfsAaron Durbin
Allow the ability for chipset or mainboard to choose to compress FSP-S in cbfs using LZMA or LZ4 routines. To accomplish this fsp_load_component() is added as an assist for performing the necessary logic and allow the caller to provide the destination selection. Since the main cbfs decompression paths are utilized add the appropriate checks for including compression algorithms under the FSP-S compression options. On picasso FSP-S (debug builds) the following savings were measured: no-compression: fsps.bin 327680 none FSP_COMPRESS_FSP_S_LZ4: fsps.bin 98339 LZ4 (327680 decompressed) -70% FSP_COMPRESS_FSP_S_LZMA: fsps.bin 71275 LZMA (327680 decompressed) -78% BUG=b:155322763,b:150746858,b:152909132 Change-Id: I8aa5d8c1cbaf4d08f38a918a9031a2570bc5247e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-26drivers/intel/fsp2_0: print soc specific GUID extension hobsJonathan Zhang
Some SoC specific hobs are of HOB_TYPE_GUID_EXTENSION. Call SoC specific soc_display_hob() to display the content as necessary. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ib4e4abe2d89b04504d1988d8d3c2fde268b5345a Reviewed-on: https://review.coreboot.org/c/coreboot/+/41565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-26drivers/intel/fsp2_0: Remove unused 'include <memrange.h>'Elyes HAOUAS
Change-Id: Ic3eb8fca22e73a0d485a6c1bf35c33b1fc606e4a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41488 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-10src: Replace remaining GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: I4614e9b02a932530fc22912b5cf502d1b699b451 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 16:33:25 +0000