drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs

This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_"  prefix.

1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
          USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
          USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
          USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE

The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.

For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.

Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.

Additionally, fixed SoC configs inclusion order alphabetically. 

BUG=b:211954778
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

2 files changed, 20 insertions, 15 deletions

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 2992b4f849..fdea4b886f 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -310,7 +310,7 @@ config FSPS_USE_MULTI_PHASE_INIT
 	  SoC users to select this Kconfig to set EnableMultiPhaseSiliconInit to enable and
 	  execute FspMultiPhaseSiInit() API.
 
-config SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM
+config USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	bool
 	help
 	  The FSP API is used to notify the FSP about different phases in the boot process.
@@ -318,12 +318,15 @@ config SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM
 	  - Post PCI enumeration
 	  - Ready to Boot
 	  - End of Firmware
-	  Select this on a platform where you want to skip calling FSP Notify
-	  `Post PCI enumeration` API. Instead use coreboot native implementations
+	  This option allows FSP to execute Notify Phase API (Post PCI enumeration).
+	  SoC users can override this config to use coreboot native implementations
 	  to perform the required lock down and chipset register configuration prior
-	  boot to payload.
+	  to executing any 3rd-party code during PCI enumeration (i.e. Option ROM).
+
+	  coreboot native implementation to skip FSP Notify Phase (Post PCI enumeration)
+	  is still WIP.
 
-config SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT
+config USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	bool
 	help
 	  The FSP API is used to notify the FSP about different phases in the boot process.
@@ -331,11 +334,12 @@ config SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	  - Post PCI enumeration
 	  - Ready to Boot
 	  - End of Firmware
-	  Select this on a platform where you want to skip calling FSP Notify `Ready to Boot`
-	  API. Instead use coreboot native implementations to perform the required lock down
-	  and chipset register configuration prior boot to payload.
+	  This option allows FSP to execute Notify Phase API (Ready to Boot).
+	  SoC users can override this config to use coreboot native implementations
+	  to perform the required lock down and chipset register configuration prior
+	  boot to payload.
 
-config SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
+config USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
 	bool
 	help
 	  The FSP API is used to notify the FSP about different phases in the boot process.
@@ -343,8 +347,9 @@ config SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
 	  - Post PCI enumeration
 	  - Ready to Boot
 	  - End of Firmware
-	  Select this on a platform where you want to skip calling FSP Notify `End of Firmware`
-	  API. Instead use coreboot native implementations to perform the required lock down
-	  and chipset register configuration prior boot to payload.
+	  This option allows FSP to execute Notify Phase API (End of Firmware).
+	  SoC users can override this config to use coreboot native implementations
+	  to perform the required lock down and chipset register configuration prior
+	  boot to payload.
 
 endif
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index 36b538ffc6..30d61c971d 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -20,7 +20,7 @@ struct fsp_notify_phase_data {
 static const struct fsp_notify_phase_data notify_data[] = {
 	{
 		.notify_phase     = AFTER_PCI_ENUM,
-		.skip             = CONFIG(SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM),
+		.skip             = !CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM),
 		.post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE,
 		.post_code_after  = POST_FSP_NOTIFY_AFTER_ENUMERATE,
 		.timestamp_before = TS_FSP_BEFORE_ENUMERATE,
@@ -28,7 +28,7 @@ static const struct fsp_notify_phase_data notify_data[] = {
 	},
 	{
 		.notify_phase     = READY_TO_BOOT,
-		.skip             = CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT),
+		.skip             = !CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT),
 		.post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE,
 		.post_code_after  = POST_FSP_NOTIFY_AFTER_FINALIZE,
 		.timestamp_before = TS_FSP_BEFORE_FINALIZE,
@@ -36,7 +36,7 @@ static const struct fsp_notify_phase_data notify_data[] = {
 	},
 	{
 		.notify_phase     = END_OF_FIRMWARE,
-		.skip             = CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
+		.skip             = !CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
 		.post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE,
 		.post_code_after  = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE,
 		.timestamp_before = TS_FSP_BEFORE_END_OF_FIRMWARE,