coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-06-12	{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support	Frans Hendriks
2019-06-04	soc/intel/braswell: Use common cpu/intel/car code	Arthur Heymans
2019-05-21	soc/intel/fsp1.1: Implement postcar stage	Arthur Heymans
2019-05-06	drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80	Frans Hendriks
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-01-16	buildsystem: Promote rules.h to default include	Kyösti Mälkki
2019-01-08	arch/x86: Unify bootblock MMX register usage	Kyösti Mälkki
2018-11-22	drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S	Frans Hendriks
2018-06-04	src/drivers: Get rid of whitespace before tab	Elyes HAOUAS
2017-06-07	src: change coreboot to lowercase	Martin Roth
2016-07-31	src/drivers: Capitalize CPU, RAM and ACPI	Elyes HAOUAS
2016-01-29	intel/skylake: Implement native Cache-as-RAM (CAR)	Subrata Banik
2015-12-03	intel/fsp: Add post codes for FSP phases	Duncan Laurie
2015-11-05	fsp1_1: pass ROM_SIZE to FSP for cacheable RO region	Aaron Durbin
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-14	fsp1_1: add verstage support	Aaron Durbin
2015-10-11	intel fsp1_1: prepare for romstage vboot verification split	Aaron Durbin
2015-10-11	intel: update common and FSP cache-as-ram parameters	Aaron Durbin
2015-09-10	FSP: Pass FSP image base address to find_fsp	Lee Leahy
2015-08-31	drivers/intel/fsp_1_1: Remove useless #ifndef/#error pairs	Alexandru Gagniuc
2015-06-24	FSP 1.1: Bring source up-to-date	Lee Leahy
2015-05-23	drivers/intel: Update FSP 1.1 Driver	Lee Leahy
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-05-12	FSP 1.1 Comparison Base	Lee Leahy