| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-03-28 | soc/intel/common/block: Add cache as ram init and teardown code | Subrata Banik |
| 2016-07-31 | Remove extra newlines from the end of all coreboot files. | Martin Roth |
| 2016-07-27 | cpu/x86: Support CPUs without rdmsr/wrmsr instructions | Lee Leahy |
| 2016-02-02 | soc/intel/common: Use SoC specific routine to read/write MTRRs | Lee Leahy |
| 2016-01-29 | intel/skylake: Implement native Cache-as-RAM (CAR) | Subrata Banik |
| 2015-12-03 | intel/fsp: Add post codes for FSP phases | Duncan Laurie |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-10-15 | cpu/mtrr.h: Fix macro names for MTRR registers | Alexandru Gagniuc |
| 2015-10-14 | fsp1_1: add verstage support | Aaron Durbin |
| 2015-10-11 | intel fsp1_1: prepare for romstage vboot verification split | Aaron Durbin |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |