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path: root/src/devices/pci_device.c
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2012-11-30Rename devices -> deviceStefan Reinauer
to match src/include/device Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1960 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30Create a a new configuration variable for PCIRonald G. Minnich
Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1947 Tested-by: build bot (Jenkins)
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
As we move to supporting other systems we need to get rid of assembly where we can. The log2 function in src/lib is identical to the assembly one (tested for all 32-bit signed integers :-) and takes about 10 ns to run as opposed to 5ns for the non-portable assembly version. While speed is good, I think we can spare the 15 ns or so we add to boot time by using the C version only. Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1928 Tested-by: build bot (Jenkins)
2012-11-20Unify use of bool config variablesStefan Reinauer
e.g. -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS This will make it easier to switch over to use the config_enabled() macro later on. Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-13cros: Inform U-Boot via fake gpio when VGA Option ROM is loadedBill Richardson
This prepares the way for vboot to inform coreboot when it needs the VGA Option ROM loaded. Coreboot can't always know when it's needed (with keyboard-based dev-mode, coreboot can't tell if we're in dev-mode or not). By the time we get to U-Boot, it's too late, so we need two extra bits - one for vboot to tell coreboot to load the Option ROM and another for coreboot to let vboot know it's been done. This change sets up the communication, but doesn't act on it just yet. Even with this CL we always load the VGA Option ROM, so there's nothing to test. There should be no user-visible change. Change-Id: Ic4e9673a3707b6605064f4879bb3e74d4412322f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: http://review.coreboot.org/1822 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-01Allow device ID arrays in the PCI driver structureVadim Bendebury
Many PCI devices share the very same driver despite having different PCI device IDs, which causes a lot of copy and paste of driver definitions. This change introduces a way to specify the array of acceptable device IDs in a single driver entry. As an example the Intel {Sandy|Ivy} Bridge SATA driver is being modified to use a single driver structure for all different SATA controller flavors, a few more Ivy Bridge IDs are being added as well. BUG=none TEST=manual . modified coreboot brought up an Ivy Bridge platform all the way to Linux login screen. Change-Id: I761c5611b93ef946053783f7a755e6c456dd6991 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/982 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-02[ChromeOS] Don't initialize VGA Option ROM in normal modeStefan Reinauer
ChromeOS features two different modes: normal mode and developer mode (aka jailbreak mode). In developer mode, we need to display a warning screen for security reasons. However, in normal mode we want to boot blazingly fast. Therefore we don't run (VGA) option ROMs, unless we have to print something on the screen before the kernel is loaded. Change-Id: I37f63d0b082a48e037e65bde2b380f9b8743ed29 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/829 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-08Don't run VGA option ROMs on S3 resume.Stefan Reinauer
This will save us a few 100 ms on resume. Change-Id: Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/715 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-03-01Use subsystem id from devicetree.cb instead of Kconfig and moveSven Schnelle
all boards to the new config scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-03Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functionsPatrick Georgi
This is so that boards can determine them on runtime based on hardware properties, if so desired. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Joseph Kellermann <Joseph.Kellermann@heitec.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16don't hardcode CONFIG_PC80_SYSTEMStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22Printing coreboot debug messages on VGA console is pretty much useless, sinceStefan Reinauer
initializing VGA happens pretty much as the last thing before starting the payload. Hence, drop VGA console support, as we did in coreboot v3. - Drop VGA and BTEXT console support. Console is meant to be debugging only, and by the time graphics comes up 99% of the risky stuff has already happened. Note: This patch does not remove hardware init but only the actual output functionality. The ragexl driver needs some extra love, but that's for another day - factor out die() and post() - drop some leftover RAMBASE < 0x100000 checks. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: QingPei Wang<wangqingpei@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-04Various cosmetic and coding style fixes in src/devices.Uwe Hermann
Also: - Improve a few code comments, fix typos, etc. - Change a few more variable types to u8/u16/u32 etc. - Make some very long lines fit into 80chars/line. - Drop a huge duplicated comment, use "@see" to refer to the other one. - Reduce nesting level a bit by restructuring some code chunks. - s/Config.lb/devicetree.cb/ in a few places. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17Various Doxygen comment fixes, typo fixes, etc.Uwe Hermann
- Fix incorrect argument names for @param entries. - Add missing @param and @return entries, partly as TODOs. - s/@returns/@return/, that's a typo. - Small whitespace fixes while I'm at it. - Drop useless @brief commands, they just clutter the comments and make them harder to read. Doxygen has an option to always use the first sentence of a Doxygen-comment as @brief automatically (should be on per default). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13Print an error and correct pci scan limits. Skip sb700 ISA DMA init if needed.Juhana Helovuo
Signed-off-by: Juhana Helovuo <juhe@iki.fi> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-17Always enable parent resources before child resources.Myles Watson
Always initialize parents before children. Move s2881 code into a driver. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-09Same conversion as with resources from static arrays to lists, exceptMyles Watson
there is no free list. Converting resource arrays to lists reduced the size of each device struct from 1092 to 228 bytes. Converting link arrays to lists reduced the size of each device struct from 228 to 68 bytes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-21Use lists instead of arrays for resources in devices to reduce memory usage.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27Since some people disapprove of white space cleanups mixed in regular commitsStefan Reinauer
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-02The error message is misleading, even for a SPEW, becauseStefan Reinauer
the slot is empty, it's NOT a bad ID (and the message is more confusing than helpful even in SPEW) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22printk_foo -> printk(BIOS_FOO, ...)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-051. Move run_bios prototype to device.hMyles Watson
2. Use time.h for get_time() and move tb_freq into functions.c 3. Move read_io and write_io to io.c and make them static 4. Make a couple of functions static in interrupt.c 5. Refactor a cast from char[] to u64 to get rid of potential alignment problems and a warning Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22This is a general cleanup patchStefan Reinauer
- drop include/part and move files to include/ - get rid lots of warnings - make resource allocator happy with w83627thg - trivial cbmem resume fix - fix payload and log level settings in abuild - fix kontron mptable for virtual wire mode - drop some dead includes and dead code. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-03improve debug output.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06Remove drivers/pci/onboard. The only purpose was for option ROMs, which areMyles Watson
now handled more generically using CBFS. Simplify the option ROM code in device/pci_rom.c, since there are only two ways to get a ROM address now (CBFS and the device) and add an exception for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05Don't try to set fixed resources. Trivial.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27Improve coreboot build output and eliminate some warnings:Uwe Hermann
- Add static and const where possible. - Turn some #warning entries into TODO comments. - Add missing prototypes. - Remove unused variables. - Fix printf arguments or cast them as needed. - Make sconfig output look better. Drop useless "PARSED THE TREE" output. - Print "(this may take a while)" while building romcc. Add missing "\n". Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watosn <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Kconfig allows you to run all PCI ROMs, VGA only, or non-VGA only.Myles Watson
Update the code to support that too. Remove an unused variable. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-21Trivial spelling corrections.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-19Add an error message if there is a zero-sized fixed resource. Fix the existingMyles Watson
example of one. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21Rewrite interrupt handling in coreboot to be more comprehensible andStefan Reinauer
more flexible. Also some minore device allocator cleanups that sneaked in. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-02Move the v3 resource allocator to v2.Myles Watson
Major changes: 1. Separate resource allocation into: A. Read Resources B. Avoid fixed resources (constrain limits) C. Allocate resources D. Set resources Usage notes: Resources which have IORESOURCE_FIXED set in the flags constrain the placement of other resources. All fixed resources will end up outside (above or below) the allocated resources. Domains usually start with base = 0 and limit = 2^address_bits - 1. I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is still there for resources. Some platforms may want to change that, but I didn't want to break anyone's board. Resources are allocated in a single block for memory and another for I/O. Currently the resource allocator doesn't support holes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30This patch unifies the use of config options in v2 to all start with CONFIG_Stefan Reinauer
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-29Fix build with CONFIG_*_ROM_RUN.Luc Verhaegen
Last commit broke it due to leftover "void" from prototype. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Luc Verhaegen <libv@skynet.be> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-29Implement native VGA Support.Luc Verhaegen
This code brings a rather complete set of VGA IO routines for whoever wants it. These consist of the by now familiar read/write/mask sets. Due to the crazy nature of VGA, an ancient standard with bits all over the place, it makes no sense to define individual registers. You need a vga register spec at hand if you want to do anything anyway. These IO routines are always exposed. It also provides code to natively set up a 640x400 VGA textmode with an 8x16 font. The native VGA mode code is behind the OPTION_VGA option, as the font really adds to the size of the compiled/compressed rom. The font is the one also present in the linux kernel, but this file is unlicensed. Another copy of this is also present in coreboot in the deprecated console/btext code. The vga console code has been cleaned up, but it still has some TODO's left open, but that's for when i finally have found the remaining issue with the epia-m. Right now, it is important to get parts of my work out already and to make the remainder managable again. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-11Trivial white space fixes so that the next patches are easier to read.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21Eliminate various issues brought up by scan-build.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-16fix typo in pci_device.c (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3Stefan Reinauer
a long time ago. This will make it easier to port v2 boards forward to v3 at some point (and other things) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-09Remove some warnings, mainly from format strings which didn't match theMyles Watson
arguments. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Changes required to the device allocator:Stefan Reinauer
- leave a hole for mmapped PCIe config space if CONFIG_PCIE_CONFIGSPACE_HOLE is set. - Mask moving bits to 32bit when resources are not supposed above 4G. Linux does not like this, even though the resource is disabled. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-11From Vincent Legoll:Stefan Reinauer
Use dev_path() to have nice debug output patch is run-time tested Trivial, thus: Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01fix typos and warnings in the device tree code (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-28In pci_device.c, the class for VGA was not tested properly, leading toRonald Hoogenboom
no VGA output from coreboot, even after the boot-rom was executed properly (CONFIG_PCI_ROM_RUN) or no boot-rom execution with CONFIG_VGA_ROM_RUN at all. According to the header file device.h, the class field of struct device is '3 bytes: (base,sub,prog-if)'. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> Acked-by: Torsten Duwe <duwe@lst.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
code is changed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-06Since a VGA console and the need to run any option ROMs areTorsten Duwe
rather independent, lift the implicit (broken) assumption that CONSOLE_VGA would also run the ROMs, and transfer it to a new config option VGA_ROM_RUN. This change is minimally intrusive, because all board configs that previously assumed CONSOLE_VGA would also run the ROMs didn't compile, they had to also specify PCI_ROM_RUN. Based on patches by Ron Minnich (fix the compile) and Luc Verhaegen (separate ROM_RUN from VGA console). Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Luc Verhaegen <libv@skynet.be> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-26Don't arbitrarily enable PERR# and SERR# for PCI devices. Marc Jones
It is platform specific. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-22Add explicit license headers to all files in src/device.Uwe Hermann
For files derived from the Linux kernel we merely add a small header which states the origin of the file and the copyright owners of the modifications to the file. We know all files from Linux are licensed under the GPLv2. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06This patch makes sure that VGA is initialized before it is used. WithoutRoman Kononov
this fix, LinuxBIOS crashes if the CONSOLE_LOG_LEVEL is high enough. Additionally, The VGA option rom will be executed if either CONFIG_PCI_ROM_RUN=1 or CONFIG_CONSOLE_VGA=1. Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support inYinghai Lu
serengeti_cheeatah git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-18fix old bug in the src/devices/pci_device.c Ronald G. Minnich
add devices for the lx and artecgroup/dbe61 point artecgroup at cs5536_lx as it is so different. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-22set up interrupt values for the southbridge, and add a function toRonald G. Minnich
manage them. Make pci_level_irq global. Add value settings for OLPC rev_a board. Comment out no-longer-needed code in olpc mainboard.c -- it is replaced by the settings in Config.lb, and the support in cs5536.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-17TypoRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-17First, a FATAL error, that blows up your BIOS, should NEVER FAIL to Ronald G. Minnich
provide more information. The printk_debug in that failure case is now a printk_error. The msm stuff is for debugging. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-021201_ht_bus0_dev0_fidvid_core.diffStefan Reinauer
https://openbios.org/roundup/linuxbios/issue41 Lord have mercy upon us. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08eric patchYinghai Lu
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-30arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> Nvidia Ck804 support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-19minor reformatLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-14CONFIG_PCI_ROM_RUNYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-14onboard pci_rom disable onboardYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-13onboard pci_onboard worksYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-13fixed a logic bugLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-13better embedded ROM support, done blindlyLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-13onboard pci_romYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-11works for PCI vga cards tooLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-10added PCI expansion ROM support,Li-Ta Lo
works for some ATI and Nvidia AGP cards now. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-27clean up VGA and Expansion ROM supportLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-23Allocating resource for Expansion ROMLi-Ta Lo
More correct resource allocation for legacy VGA on K8 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-03allocating resource for legacy VGA frame buffer, it is not 100%Li-Ta Lo
correct but it works anyway. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-25update comment according to the new DOMLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-18- First stab at getting the ppc ports building and working.Eric Biederman
- The sandpointx3+altimus has been consolidated into one directory for now. - Added support for having different versions of the pci access functions on a per bus basis if needed. Hopefully I have not broken something inadvertently. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- Bump the LinuxBIOS major versionEric Biederman
- Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- First stab at running linuxbios without the old static device tree.Eric Biederman
Things are close but not quite there yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- Updates for 64bit resource support, handling missing devices and cpus in ↵Eric Biederman
the config file git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- First pass through with with device tree enhancement merge. Most of the ↵Eric Biederman
mechanisms should be in place but don't expect anything to quite work yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06epia-m supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-08code reformatLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-24minor reformatLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-24added AGP support for AMD K8Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-05code refromat, doxidizationLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-29changed dev->enable to dev->enabled. Sorry, I am the only one who can't speakLi-Ta Lo
English in the project. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-23Doxidization, reformatLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-11- Moved hlt() to it's own header.Eric Biederman
- Reworked pnp superio device support. Now complete superio support is less than 100 lines. - Added support for hard coding resource assignments in Config.lb - Minor bug fixes to romcc - Initial support for catching the x86 processor BIST error codes. I've only seen this trigger once in production during a very suspcious reset but... - added raminit_test to test the code paths in raminit.c for the Opteron - Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED so we can tell what we have really done. - Added generic AGP/IOMMU setting code to x86 - Added an implementation of memmove and removed reserved identifiers from memcpy - Added minimal support for booting on pre b3 stepping K8 cores - Moved the checksum on amd8111 boards because our default location was on top of extended RTC registers - On the Hdama added support for enabling i2c hub so we can get at the temperature sensors. Not that i2c bus was implemented well enough to make that useful. - Redid the Opteron port so we should only need one reset and most of memory initialization is done in cpu_fixup. This is much, much faster. - Attempted to make the VGA IO region assigment work. The code seems to work now... - Redid the error handling in amdk8/raminit.c to distinguish between a bad value and a smbus error, and moved memory clearing out to cpufixup. - Removed CONFIG_KEYBOARD as it was useless. See pc87360/superio.c for how to setup a legacy keyboard properly. - Reworked the register values for standard hardware, moving the defintions from chip.h into the headers of the initialization routines. This is much saner and is actually implemented. - Made the hdama port an under clockers BIOS. I debuged so many interesting problems. - On amd8111_lpc added setup of architectural/legacy hardware - Enabled PCI error reporting as much as possible. - Enhanded build_opt_tbl to generate a header of the cmos option locations so that romcc compiled code can query the cmos options. - In romcc gracefully handle function names that degenerate into function pointers - Bumped the version to 1.1.6 as we are getting closer to 2.0 TODO finish optimizing the HT links of non dual boards TODO make all Opteron board work again TODO convert all superio devices to use the new helpers TODO convert the via/epia to freebios2 conventions TODO cpu fixup/setup by cpu type git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-15for tyan. recover from Eric B's error additions to via code :-)Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-14- Minor bugfixesEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-11 - O2, enums, and switch statements work in romccEric Biederman
- Support for compiling romcc on non x86 platforms - new romc options -msse and -mmmx for specifying extra registers to use - Bug fixes to device the device disable/enable framework and an amd8111 implementation - Move the link specification to the chip specification instead of the path - Allow specifying devices with internal bridges. - Initial via epia support - Opteron errata fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-02success. It boots as a bproc slave now.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-02IRQ setup for EPIARonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-30The epia now works.Ronald G. Minnich
Now to fix the ram ... git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-02- 1.1.4Eric Biederman
Major restructuring of hypertransport handling. Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically Updates to hard_reset handling when resetting because of the need to change hypertransport link speeds and widths. (a) No longer assume the boot is good just because we get to a hard reset point. (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the boot counter. Updates to arima/hdama mptable so it tracks the new bus numbers git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-02- Major update of the dynamic device tree so it can handleEric Biederman
* subtractive resources * merging with the static device tree * more device types than just pci - The piece to watch out for is the new enable_resources method that was needed in all of the drivers git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-01- Add back in the hard reset code from the freebios1 tree.Eric Biederman
This allows generic code to reset the box. - Update the hypertransport code to automatically calculate link widths and freequencies, and to call hard_reset if neecessary for the changes to go into effect. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21- First pass at code for generic link width and size determinationEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17- Remove excess line from pci_device.cEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17- Implement an enable method for pci devices.Eric Biederman
- Add initial support for the amd8131 - Update the mptable to something possible - hdama/Config add the amd8131 southbridge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17- pci_device.c fixes for generic pci bridges to zero the unused portion of ↵Eric Biederman
bridge resources - coherent_ht.c remove dead idle loop. - raminit.c Enable a 64MB mmio window just below 4GB git-svn-id: svn://svn.coreboot.org/coreboot/trunk@967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-12- Modify the freebios tree so the pci config space api is mostly in sync betweenEric Biederman
code that runs without ram and code that runs with ram. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-19- Cleanups on the romcc side including a pci interface that usesEric Biederman
fewer registers, and is easier to hardcode. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-24- Small step forward Linux boots and almost works...Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-21 08:23:32 +0000