coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-08-21	nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.c	Patrick Rudolph
2018-08-20	nb/intel/sandybridge: Fill in DIMM serial number	Patrick Rudolph
2018-07-02	src: Get rid of unneeded whitespace	Elyes HAOUAS
2018-04-16	device/dram/ddr3: improve XMP support	Dan Elkouby
2018-04-09	device/dram/ddr2.c: Add methods to compute to identify dram	Arthur Heymans
2017-03-10	device/dram/ddr2: Add common ddr2 spd decoder	Patrick Rudolph
2016-12-27	device/dram/ddr3: add FTB timings	Nicola Corna
2016-11-21	device/dram/ddr3: Fix calculation CRC16 of SPD	Kyösti Mälkki
2016-11-20	device/dram/ddr3: Calculate CRC16 of SPD unique identifier	Kyösti Mälkki
2016-03-21	device/dram/ddr3: fix debug output	Patrick Rudolph
2016-03-03	src/device/dram/ddr3: Parse additional information	Patrick Rudolph
2016-02-20	nb/intel/sandybridge/raminit: Add XMP support	Patrick Rudolph
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-06-23	ddr3: add missing newline	Patrick Rudolph
2015-06-23	ddr3: Fix SPD CRC calculation	Patrick Rudolph
2015-01-12	src/device: Doxygen fixes	Martin Roth
2014-12-07	ddr3: Plumber DIMM type to parsed structure.	Vladimir Serbinenko
2014-11-08	device/dram/ddr3.c: Fix sizeof on array func param overflow	Edward O'Callaghan
2014-07-29	sandy/ivybridge: Native raminit.	Vladimir Serbinenko
2013-12-17	device/dram/ddr3: Move CRC calculation in a separate function	Alexandru Gagniuc
2013-07-10	device: Fix spelling	Martin Roth
2013-06-04	DDR3: Add utilities for creating MRS commands	Alexandru Gagniuc
2013-06-03	dram: Add utilities for decoding DDR3 SPDs	Alexandru Gagniuc