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path: root/src/cpu
AgeCommit message (Expand)Author
2012-08-09Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPUKyösti Mälkki
2012-08-09AMD northbridge: copy TOP_MEM and TOP_MEM2 for distributionKyösti Mälkki
2012-08-09Synchronize rdtsc instructionsStefan Reinauer
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
2012-08-05AMD S3: Remove the hardcoded volatile positionzbao
2012-08-04Make the device tree available in the rom stageStefan Reinauer
2012-08-03Intel CPUs: Fix counting of CPU coresKyösti Mälkki
2012-08-01Intel Sandybridge: add reserved memory as resourcesKyösti Mälkki
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
2012-07-26CPU: Add option to set TCC activation offsetDuncan Laurie
2012-07-26ACPI: Add a method to notify OS to re-read _PPCDuncan Laurie
2012-07-26ACPI: Add function to write _PPC using NVSDuncan Laurie
2012-07-26USBDEBUG: buffer up to 8 bytesSven Schnelle
2012-07-26Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logsStefan Reinauer
2012-07-26Enable Microcode in CBFS for all SandyBridge/IvyBridge systemsStefan Reinauer
2012-07-25SMM: Fix state table for Intel Core2 CPUsStefan Reinauer
2012-07-25Fix comment to reference IvyBridge, tooStefan Reinauer
2012-07-25Include SandyBridge Microcode when IvyBridge is enabledStefan Reinauer
2012-07-25Fix date output in Microcode updateStefan Reinauer
2012-07-25Fix LAPIC timer on Ivy Bridge systemsStefan Reinauer
2012-07-24CPU: Set flex ratio to nominal TDP ratio in bootblockDuncan Laurie
2012-07-24SMM: Fix state save map for sandybridge and TSEGDuncan Laurie
2012-07-24SMM: Add heap region and move C handler higher in regionDuncan Laurie
2012-07-24CPU: Update ivybridge PP1 current limit valueDuncan Laurie
2012-07-24CPU: Add basic support for Nominal Configurable TDPDuncan Laurie
2012-07-24Rename cache_lbmem() to cache_ramstage()Stefan Reinauer
2012-07-24Config changes to support microcode in CBFSVadim Bendebury
2012-07-24Add microcode blob processingVadim Bendebury
2012-07-24Add code to read Intel microcode from CBFSVadim Bendebury
2012-07-24Make MAX_PHYSICAL_CPUS invisible on non-AMD boardsStefan Reinauer
2012-07-24Rename microcode include file to be model agnosticVadim Bendebury
2012-07-24Properly identify ACPI C3 states in _CST table.Duncan Laurie
2012-07-24Remove code that enables/disables VMX in coreboot on chromebooks.Ronald G. Minnich
2012-07-24MTRR: drop repetetive debug messageStefan Reinauer
2012-07-23Re-initialize Local APIC timer on APsStefan Reinauer
2012-07-22AMD CPUs: Updated CPU list in powernow_acpi.cJukka Rantala
2012-07-18AMD northbridges: drop dead codeKyösti Mälkki
2012-07-16AMD: Fix GFXUMA with 4GB or more RAMKyösti Mälkki
2012-07-16AMD MTRR: fix rounding and renamesKyösti Mälkki
2012-07-16Check for IORESOURCE_UMA_FB in MTRR setupKyösti Mälkki
2012-07-16Define global uma_memory variablesKyösti Mälkki
2012-07-14Remove useless file from building.zbao
2012-07-12Drop Kconfig VAR_MTRR_HOLE optionKyösti Mälkki
2012-07-12Fix stack assignment during CPU initializationSven Schnelle
2012-07-05Only copy real-mode section of SIPI vectorKyösti Mälkki
2012-07-05Fix the CPU index parameter passed to secondary_cpu_init().Kyösti Mälkki
2012-07-04Intel cpus: Extend cache to cover complete Flash DeviceKyösti Mälkki
2012-07-04Intel model_106cx: change CAR to model_6exKyösti Mälkki
2012-07-04Intel cpus: delete dead CAR code and whitespace fixesKyösti Mälkki
2012-07-04Intel cpus: use CPU_ADDR_BITS from Kconfig during CARKyösti Mälkki
2012-07-03AGESA F15 wrapper for Trinityzbao
2012-07-02remove CONFIG_SERIAL_CPU_INITSven Schnelle
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
2012-07-02Intel CPUs: execute microcode update only once per coreKyösti Mälkki
2012-06-19Enable Intel PECI on Model 6fx CPUsSven Schnelle
2012-06-12udelay: add missing bus frequencySven Schnelle
2012-05-30Fix the location of "Setting variable MTRR" printk.Denis 'GNUtoo' Carikli
2012-05-29Drop config variable CPU_MODEL_INDEXStefan Reinauer
2012-05-08Some more #if cleanupPatrick Georgi
2012-05-08Clean up #ifsPatrick Georgi
2012-05-03Fix register corruption during Intel Microcode updateStefan Reinauer
2012-05-02Don't include console.h in microcode.c when compiling with ROMCCStefan Reinauer
2012-05-01Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boardsStefan Reinauer
2012-05-01Move VSA support from x86 to GeodePatrick Georgi
2012-05-01Make geode_lx use the vsa from blobs repositoryPatrick Georgi
2012-04-30Fix up Sandybridge C state generation codeStefan Reinauer
2012-04-30Rework ACPI CST table generationStefan Reinauer
2012-04-27Move top level pc80 directory to drivers/Stefan Reinauer
2012-04-26microcode: print date of microcode and unify outputStefan Reinauer
2012-04-26Revamp Intel microcode update codeStefan Reinauer
2012-04-25Replace cache control magic numbers with symbolsPatrick Georgi
2012-04-22amd: Fix unused variable warningVikram Narayanan
2012-04-20Revert wbind added to the reset_vectorMarc Jones
2012-04-16S3 code in coreboot public folder.zbao
2012-04-12S3 code in vendorcode folder.zbao
2012-04-11Remove obsolete empy macro definitionRon Minnich
2012-04-06Fixes and Sandybridge support for lapic cpu initStefan Reinauer
2012-04-06Fix support for RAM-less multi-processor initKyösti Mälkki
2012-04-06Add Sandybridge/Cougar Point support to SMM relocation handlerStefan Reinauer
2012-04-06Cache 8MB flash instead of 4MBStefan Reinauer
2012-04-05Fix timer frequency detection on SandybridgeStefan Reinauer
2012-04-05Invalidate cache before first jumpStefan Reinauer
2012-04-05Update documentation in smmrelocate.S to mention TSEGStefan Reinauer
2012-04-05Add support for Intel Sandybridge CPUStefan Reinauer
2012-04-04Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
2012-04-02Apply cache-as-ram conditionally on socket mPGA604Kyösti Mälkki
2012-04-02S3 code whitespaces changes.zbao
2012-03-31Whitespace fixesPatrick Georgi
2012-03-31Intel cpus: get MAXPHYADDR at runtime for new CARKyösti Mälkki
2012-03-31Intel cpus: add hyper-threading CPU support to new CARKyösti Mälkki
2012-03-31Intel cpus: improve CPU compatibility of new CARKyösti Mälkki
2012-03-31Add support for RAM-less multi-processor initKyösti Mälkki
2012-03-31Intel cpus: apply some good programming practices in new CARKyösti Mälkki
2012-03-31Intel cpus: cache actual size of the Flash ROM deviceKyösti Mälkki
2012-03-31Intel cpus: copy model_6ex CAR codeKyösti Mälkki
2012-03-30Make MTRR min hole alignment 64MBDuncan Laurie
2012-03-30Fix MB calculation in the reporting of the MTRR holeDuncan Laurie
2012-03-30MTRR: add alternate allocation method for odd memory mapsDuncan Laurie
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