summaryrefslogtreecommitdiff
path: root/src/cpu/intel
AgeCommit message (Expand)Author
2017-03-09cpu/intel/model_6{e,f}x: Unify init filesPaul Menzel
2017-02-22src/cpu/intel: Add license headers to all filesMartin Roth
2017-01-10cpu/intel/model_6fx: Add Conroe-L to cpu_device_id listArthur Heymans
2016-12-27cpu/intel/common: Add/Use common function to set virtualizationMatt DeVillier
2016-12-18intel cache-as-ram: Move DCACHE_RAM_BASEKyösti Mälkki
2016-12-11intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setupKyösti Mälkki
2016-12-10cpu/intel/lga775: Do not select model_6ex CPUArthur Heymans
2016-12-09intel/sandybridge: Use postcar_frame for MTRR setupKyösti Mälkki
2016-12-06CPU: Declare cpu_phys_address_size() for all archKyösti Mälkki
2016-12-01romstage_handoff: remove code duplicationAaron Durbin
2016-11-20intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINITKyösti Mälkki
2016-11-20intel car: Move pre-ram stack guard lowerKyösti Mälkki
2016-11-18intel/sandybridge post-car: Redo MTRR settings and stack selectionKyösti Mälkki
2016-11-18intel post-car: Increase stacktop alignmentKyösti Mälkki
2016-11-11intel cache-as-ram: Unify stack setupKyösti Mälkki
2016-11-11intel post-car: Separate files for setup_stack_and_mtrrs()Kyösti Mälkki
2016-11-11intel/sandybridge: Use common ACPI S3 recoveryKyösti Mälkki
2016-11-09Move select UDELAY_LAPIC from nb/gm45/Kconfig to cpu/model_1067x/KconfigArthur Heymans
2016-11-08cpu/intel/socket_mPGA478MN: Add socket PArthur Heymans
2016-11-08intel post-car: Split legacy socketsKyösti Mälkki
2016-10-31lib/prog_loaders: use common ramstage_cache_invalid()Aaron Durbin
2016-10-11cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZENico Huber
2016-10-09cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4EArthur Heymans
2016-09-08Kconfig: Add option for microcode filenamesMartin Roth
2016-09-04src/cpu: Improve code formattingElyes HAOUAS
2016-08-28src/cpu: Add required space before opening parenthesis '('Elyes HAOUAS
2016-08-28src/cpu: Remove unnecessary whitespace before "\n"Elyes HAOUAS
2016-08-23src/cpu: Capitalize CPU, APIC and IOAPIC typo fixElyes HAOUAS
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
2016-07-31src/cpu: Capitalize CPUElyes HAOUAS
2016-07-31src/cpu: Capitalize ROM and RAMElyes HAOUAS
2016-07-26intel car: Use MTRR WRPROT type for XIP cacheKyösti Mälkki
2016-07-26intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZEKyösti Mälkki
2016-07-23intel/haswell: Remove useless MTRR clearKyösti Mälkki
2016-07-23intel/haswell post-car: Minor fix on MTRR settingKyösti Mälkki
2016-07-23intel/haswell: Add asmlinkage for romstage_after_car()Kyösti Mälkki
2016-07-22intel car: Unify postcodesKyösti Mälkki
2016-07-22intel car: Unify whitespace and comment fixesKyösti Mälkki
2016-07-22intel car: Remove guard on XIP_ROM_SIZEKyösti Mälkki
2016-07-22intel model_106cx: Include CAR from socket directoryKyösti Mälkki
2016-07-10intel post-car: Consolidate choose_top_of_stack()Kyösti Mälkki
2016-06-29intel/haswell: No need for ACPI S3 resume backupKyösti Mälkki
2016-06-29intel romstage: Use run_ramstage()Kyösti Mälkki
2016-06-22ACPI S3: Add common recovery codeKyösti Mälkki
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
2016-06-22intel/model_206ax: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-22intel/model_2065x: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-22intel cache-as-ram: Fix comment about MTRRsKyösti Mälkki
2016-06-21intel/model_6ex: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-21intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-21intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-18intel: Fix romstage main() with asmlinkageKyösti Mälkki
2016-06-18intel/cache_as_ram_ht.inc: Fix includeKyösti Mälkki
2016-06-18intel cache_as_ram: Fix typo in commentKyösti Mälkki
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
2016-06-17Fix some cbmem.h includesKyösti Mälkki
2016-05-06{cpu,soc}/intel: remove unused smm_init() functionAaron Durbin
2016-05-06cpu/intel/haswell: convert to using common MP and SMM initAaron Durbin
2016-05-04cpu/x86: remove BACKUP_DEFAULT_SMM_REGION optionAaron Durbin
2016-05-02cpu/x86/mp_init: remove unused callback argumentsAaron Durbin
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
2016-03-08x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
2016-02-14CPU/intel: Add missing license headersDamien Roth
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
2016-02-10cpu/intel/microcode: allow microcode to be loaded in romstageAaron Durbin
2015-12-06Remove #ifdef checks on Kconfig symbolsMartin Roth
2015-12-06fsp_model_406dx: use external microcode .h files for rangeleyMartin Roth
2015-12-02x86/smm: Initialize SMM on some CPUs one-by-oneDamien Zammit
2015-11-24cpu/intel/socket_FCBGA559: Add new socket for Atom D5xxDamien Zammit
2015-11-20fsp1_0: Remove hardcoded microcode locationsMartin Roth
2015-11-16intel/fsp_model_406dx: Load APs microcode in model_406dx_initDavid Guckian
2015-11-16intel/fsp_rangeley: Load BSP microcode in bootblockDavid Guckian
2015-11-10cpu/intel: Add socket BGA1284Marc Jones
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-31sandybridge: Disable parallel CPU initializationNico Huber
2015-10-28cpu/intel/fsp_model_206ax: Load microcode in corebootMartin Roth
2015-10-23cpu/intel: Move Power notification ASL code into `common/acpi`Paul Menzel
2015-10-22Revert "Remove sandybridge and ivybridge FSP code path"Martin Roth
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
2015-10-08arch/x86/bootblock: Do not include non-code files in bootblock.SAlexandru Gagniuc
2015-10-07x86/bootblock: Use LDFLAGS_bootblock to enable garbage collectionAlexandru Gagniuc
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
2015-10-03Remove sandybridge and ivybridge FSP code pathAlexandru Gagniuc
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
2015-09-30cpu: microcode: Use microcode stored in binary formatAlexandru Gagniuc
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
2015-09-09intel/model_2065x/Kconfig: Don't use LAPIC_MONOTONIC_TIMERMartin Roth
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
2015-08-25Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in KconfigMartin Roth
2015-07-29Add SoC specific microcode update check in ramstageRizwan Qureshi
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
2015-06-10model_2065x: Use common i945-ivy TSEG SMM init.Vladimir Serbinenko
2015-06-10model_206ax: Fix APIC map when HT is disabled.Vladimir Serbinenko
2015-06-10fsp_model_206ax: Use common i945-ivy tseg SMM init.Vladimir Serbinenko
2015-06-09stage_cache: use cbmem init hooksAaron Durbin
2015-06-09Create i945-ivy smm tseg init based on ivy code.Vladimir Serbinenko
2015-06-08Remove empty lines at end of fileElyes HAOUAS
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 10:18:18 +0000