summaryrefslogtreecommitdiff
path: root/src/cpu/intel
AgeCommit message (Expand)Author
2016-07-31src/cpu: Capitalize CPUElyes HAOUAS
2016-07-31src/cpu: Capitalize ROM and RAMElyes HAOUAS
2016-07-26intel car: Use MTRR WRPROT type for XIP cacheKyösti Mälkki
2016-07-26intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZEKyösti Mälkki
2016-07-23intel/haswell: Remove useless MTRR clearKyösti Mälkki
2016-07-23intel/haswell post-car: Minor fix on MTRR settingKyösti Mälkki
2016-07-23intel/haswell: Add asmlinkage for romstage_after_car()Kyösti Mälkki
2016-07-22intel car: Unify postcodesKyösti Mälkki
2016-07-22intel car: Unify whitespace and comment fixesKyösti Mälkki
2016-07-22intel car: Remove guard on XIP_ROM_SIZEKyösti Mälkki
2016-07-22intel model_106cx: Include CAR from socket directoryKyösti Mälkki
2016-07-10intel post-car: Consolidate choose_top_of_stack()Kyösti Mälkki
2016-06-29intel/haswell: No need for ACPI S3 resume backupKyösti Mälkki
2016-06-29intel romstage: Use run_ramstage()Kyösti Mälkki
2016-06-22ACPI S3: Add common recovery codeKyösti Mälkki
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
2016-06-22intel/model_206ax: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-22intel/model_2065x: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-22intel cache-as-ram: Fix comment about MTRRsKyösti Mälkki
2016-06-21intel/model_6ex: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-21intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-21intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-18intel: Fix romstage main() with asmlinkageKyösti Mälkki
2016-06-18intel/cache_as_ram_ht.inc: Fix includeKyösti Mälkki
2016-06-18intel cache_as_ram: Fix typo in commentKyösti Mälkki
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
2016-06-17Fix some cbmem.h includesKyösti Mälkki
2016-05-06{cpu,soc}/intel: remove unused smm_init() functionAaron Durbin
2016-05-06cpu/intel/haswell: convert to using common MP and SMM initAaron Durbin
2016-05-04cpu/x86: remove BACKUP_DEFAULT_SMM_REGION optionAaron Durbin
2016-05-02cpu/x86/mp_init: remove unused callback argumentsAaron Durbin
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
2016-03-08x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
2016-02-14CPU/intel: Add missing license headersDamien Roth
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
2016-02-10cpu/intel/microcode: allow microcode to be loaded in romstageAaron Durbin
2015-12-06Remove #ifdef checks on Kconfig symbolsMartin Roth
2015-12-06fsp_model_406dx: use external microcode .h files for rangeleyMartin Roth
2015-12-02x86/smm: Initialize SMM on some CPUs one-by-oneDamien Zammit
2015-11-24cpu/intel/socket_FCBGA559: Add new socket for Atom D5xxDamien Zammit
2015-11-20fsp1_0: Remove hardcoded microcode locationsMartin Roth
2015-11-16intel/fsp_model_406dx: Load APs microcode in model_406dx_initDavid Guckian
2015-11-16intel/fsp_rangeley: Load BSP microcode in bootblockDavid Guckian
2015-11-10cpu/intel: Add socket BGA1284Marc Jones
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-31sandybridge: Disable parallel CPU initializationNico Huber
2015-10-28cpu/intel/fsp_model_206ax: Load microcode in corebootMartin Roth
2015-10-23cpu/intel: Move Power notification ASL code into `common/acpi`Paul Menzel
2015-10-22Revert "Remove sandybridge and ivybridge FSP code path"Martin Roth
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
2015-10-08arch/x86/bootblock: Do not include non-code files in bootblock.SAlexandru Gagniuc
2015-10-07x86/bootblock: Use LDFLAGS_bootblock to enable garbage collectionAlexandru Gagniuc
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
2015-10-03Remove sandybridge and ivybridge FSP code pathAlexandru Gagniuc
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
2015-09-30cpu: microcode: Use microcode stored in binary formatAlexandru Gagniuc
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
2015-09-09intel/model_2065x/Kconfig: Don't use LAPIC_MONOTONIC_TIMERMartin Roth
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
2015-08-25Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in KconfigMartin Roth
2015-07-29Add SoC specific microcode update check in ramstageRizwan Qureshi
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
2015-06-10model_2065x: Use common i945-ivy TSEG SMM init.Vladimir Serbinenko
2015-06-10model_206ax: Fix APIC map when HT is disabled.Vladimir Serbinenko
2015-06-10fsp_model_206ax: Use common i945-ivy tseg SMM init.Vladimir Serbinenko
2015-06-09stage_cache: use cbmem init hooksAaron Durbin
2015-06-09Create i945-ivy smm tseg init based on ivy code.Vladimir Serbinenko
2015-06-08Remove empty lines at end of fileElyes HAOUAS
2015-06-05device_ops: add device_t argument to acpi_fill_ssdt_generatorAlexander Couzens
2015-06-04Remove address from GPLv2 headersPatrick Georgi
2015-06-02cbfs: new API and better program loadingAaron Durbin
2015-05-28smm: Merge configs SMM_MODULES and SMM_TSEGVladimir Serbinenko
2015-05-28Migrate fsp_206ax to SMM_MODULESVladimir Serbinenko
2015-05-28Migrate 2065x to SMM_MODULESVladimir Serbinenko
2015-05-28Migrate 206ax to SMM_MODULESVladimir Serbinenko
2015-05-28intel: Remove pstate_coord_type.Vladimir Serbinenko
2015-05-27Move TPM code out of chromeosVladimir Serbinenko
2015-05-26acpigen: Remove all explicit length trackingVladimir Serbinenko
2015-05-26speedstep: Don't supply weak get_cst_entries.Vladimir Serbinenko
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-05-19intel/haswell: Drop MONOTONIC_TIMER_MSRPatrick Georgi
2015-05-13Include back the 306ax microcode again.Vladimir Serbinenko
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
2015-05-053rdparty: Move to blobsPatrick Georgi
2015-05-05haswell: Link stage_cache_external_region into ramstage, tooSol Boucher
2015-05-04cpu: get rid of socket source codeStefan Reinauer
2015-04-30cpu/intel/haswell: remove dependency on socket_rpga989Matt DeVillier
2015-04-28Kconfig whitespace fixesMartin Roth
2015-04-28Fix some minor Kconfig issuesMartin Roth
2015-04-24fsp: Move fsp to fsp1_0Marc Jones
2015-04-22coreboot: common stage cacheAaron Durbin
2015-03-28build system: normalize linker script file namesPatrick Georgi
2015-03-17haswell: Fix monotonic timer integrationStefan Reinauer
2015-03-13cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITYAlexander Couzens
2015-03-10x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE optionKyösti Mälkki
2015-02-28cpu/intel: (non-FSP) Remove microcode updates from treeAlexandru Gagniuc
2015-02-28cpu/intel (non-FSP): Use microcode from blobs repositoryAlexandru Gagniuc
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 14:40:47 +0000