coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-01-27	cpu/intel/socket_LGA775: Drop 'select SSE'	Elyes HAOUAS
2021-10-26	cpu/x86: Introduce and use `CPU_X86_LAPIC`	Felix Held
2021-10-26	cpu/intel/socket_LGA775: Drop commented-out entries	Felix Held
2021-10-26	cpu/intel/*/Kconfig: move selection of CPU_X86_CACHE_HELPER	Felix Held
2021-10-26	cpu/x86: Introduce `CPU_X86_CACHE_HELPER`	Felix Held
2021-10-25	cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCs	Felix Held
2021-09-08	cpu/x86/tsc: Deduplicate Makefile logic	Angel Pons
2021-06-07	cpu/intel/hyperthreading: Build only for selected models	Kyösti Mälkki
2021-05-18	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	Arthur Heymans
2021-02-02	treewide [Kconfig]: Remove useless comment	Elyes HAOUAS
2021-01-28	cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZE	Arthur Heymans
2021-01-21	cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE	Elyes HAOUAS
2019-11-25	Drop superfluous C_ENVIRONMENT_BOOTBLOCK checks	Arthur Heymans
2019-11-15	nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK	Arthur Heymans
2018-06-05	nb/intel/x4x: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-02	cpu/intel/car: Prepare for some POSTCAR_STAGE support	Kyösti Mälkki
2016-12-10	cpu/intel/lga775: Do not select model_6ex CPU	Arthur Heymans
2016-06-21	intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP	Kyösti Mälkki
2016-06-21	intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP	Kyösti Mälkki
2016-06-18	intel/cache_as_ram_ht.inc: Fix include	Kyösti Mälkki
2015-05-04	cpu: get rid of socket source code	Stefan Reinauer
2013-03-07	Fix socket LGA775	Kyösti Mälkki
2012-10-30	Add support for socket LGA775	Stefan Tauner