coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-04	x86: remove cpu_incs as romstage Make variable	Aaron Durbin
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-05-04	cpu: get rid of socket source code	Stefan Reinauer
2014-12-30	intel CAR: Fix DCACHE_RAM_BASE for old sockets	Kyösti Mälkki
2014-07-05	Drop redundant select CACHE_AS_RAM	Kyösti Mälkki
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-10-07	Remove chip.h files without config structure	Kyösti Mälkki
2012-08-22	Auto-declare chip_operations	Kyösti Mälkki
2011-10-28	Get rid of the old romstage-as-bootblock ROM layout	Patrick Georgi
2010-10-15	Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.	Uwe Hermann
2010-09-30	Rename build system variables to be more intuitive, and	Patrick Georgi
2010-08-30	We call this cache as ram everywhere, so let's call it the same in Kconfig	Stefan Reinauer
2010-08-03	Drop the USE_PRINTK_IN_CAR option. It's a bogus decision to make for any user /	Stefan Reinauer
2010-06-21	This patch adds support for the Intel D810E2CB (i810e/ICH2) desktop board. Hu...	Joseph Smith
2010-06-21	Create new socket for FCPGA370 and PGA370 CPU's for CAR. Add CAR support for ...	Joseph Smith