| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-04-25 | cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE | Arthur Heymans |
| 2019-01-15 | cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup | Arthur Heymans |
| 2018-06-05 | nb/intel/pineview: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-02 | cpu/intel/car: Prepare for some POSTCAR_STAGE support | Kyösti Mälkki |
| 2017-06-28 | cpu/intel/pineview: Include speedstep | Arthur Heymans |
| 2016-12-18 | intel cache-as-ram: Move DCACHE_RAM_BASE | Kyösti Mälkki |
| 2016-07-22 | intel model_106cx: Include CAR from socket directory | Kyösti Mälkki |
| 2015-11-24 | cpu/intel/socket_FCBGA559: Add new socket for Atom D5xx | Damien Zammit |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |