| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-10-26 | cpu/x86: Introduce and use `CPU_X86_LAPIC` | Felix Held |
| 2021-10-26 | cpu/x86: Introduce `CPU_X86_CACHE_HELPER` | Felix Held |
| 2021-10-25 | cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCs | Felix Held |
| 2021-09-08 | cpu/x86/tsc: Deduplicate Makefile logic | Angel Pons |
| 2021-06-07 | cpu/intel/hyperthreading: Build only for selected models | Kyösti Mälkki |
| 2021-05-18 | cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y | Arthur Heymans |
| 2019-05-25 | nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK | Arthur Heymans |
| 2019-01-15 | cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup | Arthur Heymans |
| 2018-06-05 | nb/intel/pineview: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-02 | cpu/intel/car: Prepare for some POSTCAR_STAGE support | Kyösti Mälkki |
| 2017-06-28 | cpu/intel/pineview: Include speedstep | Arthur Heymans |
| 2016-07-22 | intel model_106cx: Include CAR from socket directory | Kyösti Mälkki |
| 2015-11-24 | cpu/intel/socket_FCBGA559: Add new socket for Atom D5xx | Damien Zammit |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |