| Age | Commit message (Expand) | Author |
|---|---|---|
| 2011-08-04 | cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. | Keith Hui |
| 2010-10-16 | Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory. | Keith Hui |
| 2010-10-15 | Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. | Uwe Hermann |
| 2010-10-13 | Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x. | Keith Hui |
| 2010-10-12 | Add missing include of model_6bx for slot_1. | Keith Hui |
| 2010-10-06 | Convert all Intel 440BX boards to Cache-as-RAM (CAR). | Uwe Hermann |
| 2010-09-30 | Rename build system variables to be more intuitive, and | Patrick Georgi |
| 2010-05-14 | license header fixes | Nils Jacobs |
| 2010-03-05 | Add proper Slot 1 CPU support code/infrastructure. | Keith Hui |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |