| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2014-12-30 | intel CAR: Fix DCACHE_RAM_BASE for old sockets | Kyösti Mälkki |
| 2014-07-05 | Drop redundant select CACHE_AS_RAM | Kyösti Mälkki |
| 2014-01-16 | cpu/intel: Make all Intel CPUs load microcode from CBFS | Alexandru Gagniuc |
| 2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
| 2010-10-15 | Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. | Uwe Hermann |
| 2010-10-06 | Convert all Intel 440BX boards to Cache-as-RAM (CAR). | Uwe Hermann |
| 2010-05-14 | license header fixes | Nils Jacobs |
| 2010-03-05 | Add proper Slot 1 CPU support code/infrastructure. | Keith Hui |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |