coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-06-21	cpu/intel/{haswell,model_206{5,a}x}: Use MSR_CORE_THREAD_COUNT for msr at 0x35	Elyes HAOUAS
2019-01-22	cpu/intel/model_206ax: Use parallel MP init	Arthur Heymans
2018-10-30	src: Add missing include <stdint.h>	Elyes HAOUAS
2018-10-11	src: Move common IA-32 MSRs to <cpu/x86/msr.h>	Elyes HAOUAS
2018-09-26	cpu/intel/model_206ax: detect number of MCE banks	Dan Elkouby
2018-07-28	intel/sandybridge: Don't hardcode platform type	Patrick Rudolph
2018-04-11	Revert "model_206ax: Use parallel MP init"	Arthur Heymans
2018-04-11	model_206ax: Use parallel MP init	Arthur Heymans
2018-04-10	cpu/intel/sandybridge: Put stage cache into TSEG	Arthur Heymans
2017-03-16	cpu/intel: Indent with tabs	Lee Leahy
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-28	Migrate 206ax to SMM_MODULES	Vladimir Serbinenko
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2013-05-10	Drop prototype guarding for romcc	Stefan Reinauer
2013-02-09	speedstep: Deduplicate some MSR identifiers	Patrick Georgi
2012-07-26	CPU: Add option to set TCC activation offset	Duncan Laurie
2012-07-25	Fix comment to reference IvyBridge, too	Stefan Reinauer
2012-07-24	CPU: Set flex ratio to nominal TDP ratio in bootblock	Duncan Laurie
2012-07-24	CPU: Update ivybridge PP1 current limit value	Duncan Laurie
2012-07-24	CPU: Add basic support for Nominal Configurable TDP	Duncan Laurie
2012-04-05	Add support for Intel Sandybridge CPU	Stefan Reinauer