| Age | Commit message (Expand) | Author |
|---|
| 2021-02-11 | src: Remove unused <arch/cpu.h> | Elyes HAOUAS |
| 2020-10-20 | cpu/intel/model_{2065x,206ax}: fix AES-NI locking | Michael Niewöhner |
| 2020-10-16 | include/cpu/x86: introduce new helper for (un)setting MSRs | Michael Niewöhner |
| 2020-07-26 | cpu/intel/model_206ax: Clean up includes | Elyes HAOUAS |
| 2020-07-09 | cpu/intel/model_206ax/finalize.c: Drop dead code | Angel Pons |
| 2020-05-13 | src: Remove unused '#include <stdint.h>' | Elyes HAOUAS |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-04-04 | src/cpu: Use SPDX for GPL-2.0-only files | Angel Pons |
| 2020-03-04 | cpu/intel/model_206ax: Lock MSR on all cores | Patrick Rudolph |
| 2019-10-31 | cpu/x86: make set_msr_bit publicly available | Michael Niewöhner |
| 2019-09-10 | AUTHORS: Move src/cpu/intel copyrights into AUTHORS file | Martin Roth |
| 2019-06-22 | src/cpu: Use 'include <stdlib.h>' when appropriate | Elyes HAOUAS |
| 2018-11-12 | src: Remove unneeded include "{arch,cpu}/cpu.h" | Elyes HAOUAS |
| 2018-10-05 | src: Fix MSR_PKG_CST_CONFIG_CONTROL register name | Elyes HAOUAS |
| 2018-08-09 | src/cpu: Fix typo | Elyes HAOUAS |
| 2017-03-16 | cpu/intel: Add int to unsigned | Lee Leahy |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-02-11 | cpu/intel: >= nehalem: add comments to msr finalize's | Alexander Couzens |
| 2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
| 2013-02-09 | speedstep: Deduplicate some MSR identifiers | Patrick Georgi |
| 2012-11-12 | Initialize the VMX MSR | Marc Jones |
| 2012-11-12 | Revert "Remove code that enables/disables VMX in coreboot on chromebooks." | Marc Jones |
| 2012-11-07 | Leave power control registers unlocked | Sameer Nanda |
| 2012-07-24 | Remove code that enables/disables VMX in coreboot on chromebooks. | Ronald G. Minnich |
| 2012-04-05 | Add support for Intel Sandybridge CPU | Stefan Reinauer |
