| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2014-12-02 | Replace hlt with halt() | Patrick Georgi |
| 2014-01-15 | nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash | Kyösti Mälkki |
| 2013-03-22 | x86: Unify arch/io.h and arch/romcc_io.h | Stefan Reinauer |
| 2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
| 2012-07-26 | Enable Microcode in CBFS for all SandyBridge/IvyBridge systems | Stefan Reinauer |
| 2012-07-24 | CPU: Set flex ratio to nominal TDP ratio in bootblock | Duncan Laurie |
| 2012-07-24 | Add code to read Intel microcode from CBFS | Vadim Bendebury |
| 2012-07-24 | Rename microcode include file to be model agnostic | Vadim Bendebury |
| 2012-04-26 | Revamp Intel microcode update code | Stefan Reinauer |
| 2012-04-05 | Add support for Intel Sandybridge CPU | Stefan Reinauer |
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index : coreboot.git | |
| my copy of coreboot | User & |
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