coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-06-05	cpu/intel/model_206ax: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-05	cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support	Arthur Heymans
2018-04-10	cpu/intel/sandybridge: Put stage cache into TSEG	Arthur Heymans
2017-06-09	cpu/intel/model_206ax: Use tsc monotonic timer	Patrick Rudolph
2016-12-27	cpu/intel/common: Add/Use common function to set virtualization	Matt DeVillier
2016-06-22	intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP	Kyösti Mälkki
2015-09-30	cpu: microcode: Use microcode stored in binary format	Alexandru Gagniuc
2015-09-04	x86: remove cpu_incs as romstage Make variable	Aaron Durbin
2015-06-09	Create i945-ivy smm tseg init based on ivy code.	Vladimir Serbinenko
2015-05-28	Migrate 206ax to SMM_MODULES	Vladimir Serbinenko
2014-10-16	ACPI: Remove CONFIG_GENERATE_ACPI_TABLES	Vladimir Serbinenko
2012-11-27	Get rid of drivers class	Patrick Georgi
2012-09-05	buildsystem: Make CPU microcode updating more configurable	Alexandru Gagniuc
2012-04-05	Add support for Intel Sandybridge CPU	Stefan Reinauer