| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-05-09 | cougar_canyon2: Switch CPU/NB/SB to the shared FSP code | Martin Roth |
| 2014-04-26 | Rename coreboot_ram stage to ramstage | Furquan Shaikh |
| 2014-03-16 | Make POST device configurable. | Idwer Vollering |
| 2014-01-15 | Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR | Kyösti Mälkki |
| 2013-12-04 | Add the Intel FSP 206ax CPU core support | Marc Jones |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
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