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path: root/src/cpu/intel/car
AgeCommit message (Expand)Author
2024-02-18arch to cpu: Add SPDX license headers to Kconfig filesMartin Roth
2024-02-08cpu/x86/64bit: Turn jumping to long mode into a macroArthur Heymans
2023-09-14x86: Add .data section support for pre-memory stagesJeremy Compostella
2023-08-05src/*/post_code.h: Change post code prefix to POSTCODEYuchen He
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
2022-12-17Add option to use Ada code in romstageJeremy Compostella
2022-12-16cpu/intel: Fix clearing MTRR for clang 64bitArthur Heymans
2022-11-23cpu/intel/car: Define post codesMartin Roth
2022-11-22src/cpu: Remove unnecessary space after castsElyes Haouas
2022-10-26cpu/intel: Clean up includesElyes Haouas
2022-10-06cpu/intel/car/romstage.c: Clean up includes and add <types.h>Elyes Haouas
2022-07-14arch/x86: Mark prepare_and_run_postcar noreturnArthur Heymans
2022-06-07arch/x86: Add a common romstage entryArthur Heymans
2022-05-16arch/x86/postcar_loader.c: Change prepare_and_run_postcar signatureArthur Heymans
2022-03-08timestamps: Rename timestamps to make names more consistentJakub Czapiga
2021-07-07cpu/intel/car/core2/cache_as_ram: Add x86_64 supportPatrick Rudolph
2021-07-06cpu/intel/car/p4: Add x86_64 supportArthur Heymans
2021-07-05cpu/intel/car/p4-netburst: Prepare for x86_64Arthur Heymans
2021-06-01cpu/intel/car/romstage.c: Drop unused function argumentArthur Heymans
2021-01-07arch/x86: Move prologue to .init sectionKyösti Mälkki
2020-11-02cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmodePatrick Rudolph
2020-07-26cpu/intel/car/romstage.c: Remove unused <bootblock_common.h>Elyes HAOUAS
2020-06-15cpu/intel: Remove obsolete comment in CAR setupKyösti Mälkki
2020-06-13cpu/intel/car: Use symbols for CAR MTRR setupKyösti Mälkki
2020-06-06src: Remove unused 'include <cpu/x86/mtrr.h>'Elyes HAOUAS
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-04src/cpu: Use SPDX for GPL-2.0-only filesAngel Pons
2019-12-17cpu/intel: Remove ROMCC header guards and codeElyes HAOUAS
2019-12-14bootblock: Provide some common prototypesKyösti Mälkki
2019-11-25cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
2019-11-25Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans
2019-11-20cpu/intel/car: Add EC software sync to Intel romstageTim Wawrzynczak
2019-11-15nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
2019-11-12arch/x86/car.ld: Rename suffix _start/_endArthur Heymans
2019-11-04cpu/intel/car/p4-netburst: Remove delay loopsKyösti Mälkki
2019-10-28cpu/intel/car: Correctly cache the bootblock with C_ENVIRONMENT_BOOTBLOCKArthur Heymans
2019-09-10AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth
2019-08-26intel/car: Use common TS_START_ROMSTAGEKyösti Mälkki
2019-08-26lib/bootblock: Add simplified entry with basetimeKyösti Mälkki
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
2019-08-22arch/x86: Add <arch/romstage.h>Kyösti Mälkki
2019-08-21cpu/intel/car: Make stack guards more useful on C_ENV_BOOTBLOCKArthur Heymans
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
2019-08-15cpu/x86/smm: Promote smm_memory_map()Kyösti Mälkki
2019-08-15arch/x86: Add postcar_frame_common_mtrrs()Kyösti Mälkki
2019-08-15cpu/intel: Refactor platform_enter_postcar()Kyösti Mälkki
2019-06-21cpu: Add missing #include <commonlib/helpers.h>Elyes HAOUAS
2019-04-21cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCKArthur Heymans
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-02-10cpu/intel/car/*/cache_as_ram.S: Add brackets around operandArthur Heymans
2019-01-17cpu/intel/car: Remove unneeded white spaceElyes HAOUAS
2019-01-15cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setupArthur Heymans
2019-01-14cpu/intel/car/non-evict: Update microcode in CAR setupArthur Heymans
2019-01-13arch/x86: Drop Kconfig AP_SIPI_VECTORKyösti Mälkki
2019-01-13cpu/intel/car/p4: Update microcode in CAR setupArthur Heymans
2019-01-09cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans
2019-01-08cpu/intel/car/bootblock.c: Report BIST failuresArthur Heymans
2019-01-08cpu/intel/car: Enable use of C_ENVIRONMENT_BOOTBLOCKArthur Heymans
2019-01-08cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCKKyösti Mälkki
2018-12-30arch/x86: Add CAR stack location symbolsKyösti Mälkki
2018-12-30cpu/intel/car: Drop remains of setup_stack_and_mtrrs()Kyösti Mälkki
2018-12-28soc/intel: Drop romstage_after_car()Kyösti Mälkki
2018-12-24car/non-evict/exit_car.S: Use tabs instead of white spacesElyes HAOUAS
2018-12-21car/non-evict/cache_as_ram.S: Use tabs instead of spacesArthur Heymans
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-10-04cpu/intel/car: Fix typoElyes HAOUAS
2018-09-18cpu/*/car: fix ancient URL explaining XIP range run-time calculationStefan Tauner
2018-08-13cpu/intel/car: Align the stack to 16 bytes before romstage_mainArthur Heymans
2018-06-27cpu/intel/p4-netburst: skip caching rom on model_fxxArthur Heymans
2018-06-27x86/car: Replace reference of copy_and_run locationKyösti Mälkki
2018-06-17nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki
2018-06-17cpu/intel/car/p3: Use variable MTRR countKyösti Mälkki
2018-06-17cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki
2018-06-17cpu/intel/car: Remove obsolete filesKyösti Mälkki
2018-06-05cpu/intel/car/non-evict: Improve a few thingsArthur Heymans
2018-06-05cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE supportArthur Heymans
2018-06-05cpu/intel/car/core2: Improve a few thingsArthur Heymans
2018-06-05cpu/intel/car/core2: Prepare for POSTCAR_STAGE supportArthur Heymans
2018-06-02cpu/intel/car: Prepare for some POSTCAR_STAGE supportKyösti Mälkki
2018-06-02aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INITKyösti Mälkki
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
2017-09-12cpu/intel/car/cache_as_ram.inc: Fix long standing issuesKeith Hui
2017-09-12cpu/intel/car/cache_as_ram.inc: Remove unused codeKeith Hui
2017-09-12cpu/intel/car/cache_as_ram.inc: Remove broken HT codeKeith Hui
2017-09-08intel/car: Fix stack guard placementKyösti Mälkki
2017-06-28cpu/*: Add whitespace around '<<'Elyes HAOUAS
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
2017-03-16cpu/intel: Fix the spacing issuesLee Leahy
2017-03-16cpu/intel: Indent with tabsLee Leahy
2016-12-11intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setupKyösti Mälkki
2016-11-20intel car: Move pre-ram stack guard lowerKyösti Mälkki
2016-11-11intel cache-as-ram: Unify stack setupKyösti Mälkki
2016-11-11intel post-car: Separate files for setup_stack_and_mtrrs()Kyösti Mälkki
2016-11-08intel post-car: Split legacy socketsKyösti Mälkki
2016-09-04src/cpu: Improve code formattingElyes HAOUAS
2016-08-23src/cpu: Capitalize CPU, APIC and IOAPIC typo fixElyes HAOUAS
2016-07-26intel car: Use MTRR WRPROT type for XIP cacheKyösti Mälkki
2016-07-22intel car: Unify postcodesKyösti Mälkki
2016-07-22intel car: Unify whitespace and comment fixesKyösti Mälkki
2016-07-22intel car: Remove guard on XIP_ROM_SIZEKyösti Mälkki
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