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cache_as_ram.inc
Age
Commit message (
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Author
2010-06-07
replace outb -> port 0x80 with post_code() in some places.
Stefan Reinauer
2010-04-21
* clean up all but two warnings on artecgroup dbe61
Stefan Reinauer
2010-04-09
Drop ASM_CONSOLE_LOGLEVEL from LX car code. We do output in C in copy_and_run /
Stefan Reinauer
2010-04-01
-Â get rid of ASM_CONSOLE_LOGLEVEL except in two assembler files.
Stefan Reinauer
2010-02-09
Allow building images with different prefixes (ie. normal/romstage,
Patrick Georgi
2010-01-26
- Clean up and comment writing of MSRs for cache control (Backport from v3)
Edwin Beasant
2009-10-03
Remove:
Patrick Georgi
2009-08-11
cpu/amd/model_lx used its own routine for copying coreboot_ram. This
Patrick Georgi
2009-06-30
This patch unifies the use of config options in v2 to all start with CONFIG_
Stefan Reinauer
2008-10-22
Speed up copying coreboot to ram by using "movsl" instead of "movsb".
Jens Rottmann
2008-01-18
Rename almost all occurences of LinuxBIOS to coreboot.
Stefan Reinauer
2008-01-18
Please bear with me - another rename checkin. This qualifies as trivial, no
Stefan Reinauer
2007-05-22
Add missing license headers, minor cosmetic fixes in existing headers.
Uwe Hermann
2007-05-05
This is the final patch to enable the msm800sev to build. This patch
Ronald G. Minnich
2007-05-04
This patch adds support for the AMD Geode LX CPU. (rediffed)
Marc Jones