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Update memory array handle for SMBIOS type 19.
TEST=Execute "dmidecode -t 19" to check if memory array handle is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I49078b870bac3c6162913b91651ec09632800f1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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SMBIOS has a field to display the cache size, which is currently
set to UNKNOWN unconditionally, multiply the cache size of L1 and L2
by the number of cores.
TEST=Execute "dmidecode -t 7" to check if the cache information
is correct for Deltalake platform
Change-Id: Ieeb5d3346454ffb2291613dc2aa24b31d10c2e04
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46068
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables bootblock compression on SC7180. In my tests, that
makes it boot roughly 10ms faster (which isn't much, but... might as
well take it).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ibbe06eeb05347cc77395681969e6eaf1598b4260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45855
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update embedded controller firmware version for SMBIOS type 0.
TEST=Execute "dmidecode -t 0" to check if the ec version is correct
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ibd5ee27a1b8fa4e5bc66e359d3b62e052e19e8a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add socket designation in type 4 smbios.
TEST=Execute "dmidecode -t 4" to check if the socket designation is correct
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Icfdc201bd5b5921816bdce6c009a9db48c997e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This fixes non-emulation platforms as those are using 32bit code
after the bootblock_crt0 entry, like setting up CAR and updating
microcode, which isn't yet converted to support long mode.
This is a noop for the only supported x86_64 platform and all
x86_32 platforms.
Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add Thread Count in SMBIOS type 4 "Processor Information".
Modify Thread Count 2 according to SMBIOS spec, it should
be the number of threads per processor socket.
TEST="dmidecode -t4" to check.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I0e00ba706eecdc850a2c6a4d876a7732dcc8f755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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In case of 64K bootblock the pagetables don't fit, as the CBFS header
also needs a few bytes.
Fixes build error on platforms that use 64KiB bootblock.
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I854c5f575e2376827a366cca8d25682c4d90bc8f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37394
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Nearly every x86 platform uses the same arch for all stages. The only
exception is Picasso. So, factor out redundant symbols from the rest.
Alder Lake is not yet complete, so it has been skipped for now.
Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Though only one platform uses it, this will save some redundancy.
Change-Id: Ic151efe5dd9b7c89f779ac3e10c3a045f07221d3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Adds support for loading Linux kernels through FIT payloads. This has
been implemented as an assembly function in order to simplify dealing
with some of the intricacies of loading a kernel (such as needing to
jump to the kernel in ARM mode and the kernel ABI).
TEST: Booted a FIT image containing a 5.4 kernel and initramfs on the
Beaglebone Black.
Change-Id: I7dbf9467665ec17447cec73676763844b4be4764
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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ddr_frequency is ambiguous and is interpreted differently in several
places. Instead of renaming this field, this deprecates it and adds
two new fields with unambiguous naming, max_speed_mts and
configured_speed_mts. smbios.c falls back to using ddr_frequency
when either of these fields are 0.
The same value was being used for both configured memory speed and
max memory speed in SMBIOS type 17, which is not accurate when
configured speed is not the max speed.
BUG=b:167218112
TEST=Boot ezkinil, no change to dmidecode -t17
Change-Id: Iaa75401f9fc33642dbdce6c69bd9b20f96d1cc25
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44549
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The BT instruction stores its result in CF and not ZF so use the
correct jump instruction.
This fixes a hang in postcar on CPUs lacking support for this
instruction. This concerns older pre-SSE2 hardware.
Change-Id: I704e3c579150fb9b9a292ef0e83050e7bf7cb078
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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It seems that GCC's LTO doesn't like the way we implement
DECLARE_OPTIONAL_REGION(). This patch changes it so that rather than
having a normal DECLARE_REGION() in <symbols.h> and then an extra
DECLARE_OPTIONAL_REGION() in the C file using it, you just say
DECLARE_OPTIONAL_REGION() directly in <symbols.h> (in place and instead
of the usual DECLARE_REGION()). This basically looks the same way in the
resulting object file but somehow LTO seems to like it better.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6096207b311d70c8e9956cd9406bec45be04a4a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: Ic86d2e6ad00cf190a2a728280f1a738486cb18c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The code can only be compiled as x86_32. Mark it as such to fix errors
in the x86_64 assembler. The caller has to make sure to call this code
in protected mode only.
Tested on HP Z220:
* Still boots on x86_32.
Change-Id: I4c0221fb3886b586c22fe05e36109fcdc20b7eed
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The GDT loading did work fine on x86_64 a few months ago, but today it
only works in QEMU, but not on real hardware or KVM-enabled QEMU. This
might be related to toolchain changes.
Use 64bit GDT loading on x86_64 and force the assembler to generate a
64bit address load on the GDT. This will make sure no 32bit (signed)
displacement op is being generated, which points to the wrong address
in longmode.
Verified using readelf and made sure no R_X86_64_32S relocation symbol
is emitted. Disassembled the romstage ELF and made sure the GDT address
is 64bit in size.
Tested on QEMU and KVM-enabled QEMU: Doesn't crash any more on KVM.
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Change-Id: Ia824f90d9611e6e8db09bd62a05e6f990581f09a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Compiler's instrumentation cannot insert asan memory checks in
case of memory functions like memset, memcpy and memmove as they
are written in assembly.
So, we need to manually check the memory state before performing
each of these operations to ensure that ASan is triggered in case
of bad access.
Change-Id: I2030437636c77aea7cccda8efe050df4b77c15c7
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Enable ASan in ramstage if ASAN is selected in menuconfig for an
x86 platform.
Change-Id: Id5b3dc18368a5da6bdc70c84527b95d1688dc19f
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44259
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds ASan support to romstage on x86 architecture.
A Kconfig option is added to enable ASan in romstage. Compiler
flags are updated. A memory space representing the shadow region
is reserved in linker section. And a function call to asan_init()
is added to initialize shadow region when romstage loads.
Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This patch adds address sanitizer module to the library and reserves
a linker section representing the shadow region for ramstage. Also,
it adds an instruction to initialize shadow region on x86
architecture when ramstage is loaded.
Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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* On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode.
* Add a helper function to jump to arbitrary code in protected mode,
similar to the real mode call handler.
* Doesn't affect existing x86_32 code.
* Add a macro to cast pointer to uint32_t that dies if it would overflow
on conversion
Tested on QEMU Q35 using SeaBIOS as payload.
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Implements fit_payload_arch for the arm (aarch32) architecture, so that
FIT images can be used. The implementation is very similar to the
existing implementations for arm64 and riscv, and has mostly been
lifted from these other ports.
TEST: Booted Beaglebone Black (in progress port, to be submitted soon!)
with a FIT image containing a 5.4 kernel, dtb and initramfs.
Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: Iae1e875b466f8a195653d897efa1b297c61ad0a5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41912
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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INVD is called below so if postcar is running in a cached environment
it needs to happen.
NOTE: postcar cannot execute in a cached environment if clflush is not
supported!
Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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* Add support for loading GDT on x86_64.
* Add x86_64 assembly code to do the same as the x86_32 code.
* Separate x86_32 and x86_64 code.
Tested on qemu x86_32 and x86_64 using additional MTRRs.
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30500
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I714247da261d4dd1b6a722436d71404f9862e958
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Fix multiple issues allowing to boot until "Payload not loaded":
* The FMAP_CACHE was placed in memory mapped flash
- Place the FMAP_CACHE in DRAM.
* The FMAP_CACHE was overlapping the BOOTBLOCK, which has a default size
of 128KiB.
- Increase the bootblock size in memlayout to 128KiB to match the FMAP.
* The heap in bootblock wasn't usable.
- Add a linking check in armv7 common bootblock to relocate itself to
the linked address.
* A FIT payload couldn't be compiled in as the POSTRAM_CBFS_CACHE was
missing.
- Add the POSTRAM_CBFS_CACHE to memlayout.
* The coreboot log is spammed with missing timestamp table error messages
- Add TIMESTAMP table to memlayout.
Tested on QEMU armv7 vexpress.
Change-Id: Ib9357a5c059ca179826c5a7e7616a5c688ec2e95
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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TEST=Execute "dmidecode -t 4" to check if the processor information is correct for Deltalake platform
Change-Id: I5d075bb297f2e71a2545ab6ad82304a825ed7d19
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The `smbios.c` file is rather long. To improve navigability, place weak
function definitions on a separate compilation unit.
Change-Id: Idd2a4ba52b6b23aad8fd63e66ffa747d49ea713d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Most of `smbios_fill_dimm_manufacturer_from_id()` is noise. Factor the
switch into its own function to improve readability.
Change-Id: Ia0757c01572709d16589a4ed622ca2d2cb69dda2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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We can reduce the amount of duplicated code with a ternary operator.
Change-Id: I8be95a62c54749d39e3e8821abd46d9f467a5a49
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Put `__weak` at the beginning of functions and reflow lines to leverage
the increased line width of 96 characters.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I3a5fd2d4344b83e09f89053c083ec80aa297061e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The `GetPhysicallyInstalledSystemMemory` API call, at least on Windows
10, returns an error if SMBIOS tables are invalid. Various tools use
this API call and don't operate correctly if this fails. For example,
the "Intel Processor Diagnostic Tool" program is affected.
Windows then guesses the physical memory size by accumulating entries
from the firmware-provided memory map, which results in a total memory
size that is slightly lower than the actual installed memory capacity.
To fix this issue, add the handle to a type 16 entry to all type 17
entries.
Add new fields to struct memory_info and fill them in Intel common code.
Use the introduced variables to fill type 16 in smbios.c and provide
a handle to type 17 entries.
Besides keeping the current behaviour on intel/soc/common platforms, the
type 16 table is also emitted on platforms that don't explicitly fill
it, by using the existing fields of struct memory_info.
Tested on Windows 10:
The GetPhysicallyInstalledSystemMemory API call doesn't return an error
anymore and the installed memory is now being reported as 8192 MiB.
Change-Id: Idc3a363cbc3d0654dafd4176c4f4af9005210f42
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Fill in the new fields introduced with version 3.0 and install the new
entry point structure identified by _SM3_.
Tested on Linux 5.6 using tianocore as payload:
Still able to decode the tables without errors.
Change-Id: Iba7a54e9de0b315f8072e6fd2880582355132a81
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove the obscure path in source code, where ACPI S3 resume
was prohibited and acpi_resume() would return and continue
to BS_WRITE_TABLES.
The condition when ACPI S3 would be prohibited needs to be
checked early in romstage already. For the time being, there
has been little interest to have CMOS option to disable
ACPI S3 resume feature.
Change-Id: If5105912759427f94f84d46d1a3141aa75cbd6ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Make an empty macro for dcache_apply_all for code running in userspace
so that we don't hang the system.
BUG=b:161554141
TEST=Run board through a bunch of recovery cycles.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3dc0f40dfe4d4a699528068154eee2d3c23d3d74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Mark the CPU as enabled and the socket as populated.
EDK2 tests these flags before further reading this structure.
Change-Id: Ic545bb47c502cb9d2352ba6d43eaed8c97229c02
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43703
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implement type 19 by accumulating the DRAM dimm size found in cbmem's
CBMEM_ID_MEMINFO structure. This seems common on x86 where the
address space always starts at 0.
At least EDK2 uses this table in the UI and shows 0 MB DRAM if not
present.
Change-Id: Idee8b8cd0b155e14d62d4c12893ff01878ef3f1c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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Change-Id: I95c40acb2fb390c50c8d1af9dd44999f9d57c2d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It's not stricly related to spinlocks. If defined, a better
location should be found and the name collisions with other
barrier() defined in nb/intel solved.
Change-Id: Iae187b5bcc249c2a4bc7bee80d37e34c13d9e63d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43810
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's not related to spinlocks and the actual implementation
was also guarded by CONFIG(SMP).
With a single call-site in x86-specific code, empty stubs
for other arch are currently not necessary.
Also drop an unused included on a nearby line.
Change-Id: I00439e9c1d10c943ab5e404f5d687d316768fa16
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43808
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as
reset register in FADT. How unsurprising. We might as well use that
information to automatically fill in the FADT accordingly. So, do it.
To avoid having x86-specific code under arch-agnostic `acpi/`, create a
new optional `arch_fill_fadt` function, and override it for x86 systems.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Change-Id: I5a36f5729a1a5ad5819ebb3c46b775ba52237d65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42080
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found using:
diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<'
Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Files found using:
diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<'
Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I8280d29b9a7bc835c2cb7e3e3dfca70768672a5f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Code has evolved such that there seems to be little
use for global definition of cbmem_top_chipset().
Even for AMD we had three different implementations.
Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's useful to see the stack when an exception happens so you can see
the variables on the stack, and also manually recreate the back trace.
If you need to recreate the back trace, you will need to add
-fno-omit-frame-pointer to the CFLAGS.
BUG=b:159081993
TEST=Caused an exception and saw the stack dumped. Then I manually
recreated the back trace.
0xcc6fff6c: 0xcc6ce02e <- 0xcc6ce02e is in dev_initialize
0xcc6fff68: 0xcc6fff88 <-- frame 1
0xcc6fff64: 0x00000005
0xcc6fff60: 0x000000dc
0xcc6fff5c: 0x00000000
0xcc6fff58: 0x00000200
0xcc6fff54: 0x00000000
0xcc6fff50: 0x00000400
0xcc6fff4c: 0xcc6d72d4 <- 0xcc6d72d4 is in setup_default_ebdad
0xcc6fff48: 0xcc6fff68 <-ebp
0xcc6fff44: 0x00000005
0xcc6fff40: 0xcc6f571c <-esp
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3822ea7aa23202ecc98612850402eeb4b1f7b5ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I9b5589d4596eead83a5897b083ccb85ef05a03d5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43270
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I23f9aa969febe58dd3842e6a7cc75a6777b90b17
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43255
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This was specifically needed for vboot with psp_verstage, but adding
it to always be built into bootblock if needed like memcpy & memset
makes sense.
TEST=Build & boot trembyle
BUG=None
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ib724aaf1492edf053a593b42107684b7bf896592
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The tlbimvaa operation (invalidate unified TLB by MVA, all address
space identifiers) is only available on armv7 processors that support
Multiprocessing Extensions. When used on processors that do not support
the extensions it causes an "undefined instruction" exception.
This patch changes the MMU table entry filling code to use the tlbimva
(invalidate unified TLB entry by MVA and address space identifier)
operation for invalidating TLB entries, which is supported on all armv7
processors.
As address space identifiers are not used in TLB entries in coreboot
(all entries are set as global), these two operations can safely be
used interchangeably. The ASID value supplied to the operation is not
checked for global TLB entries.
More information as well as the data formats for the tlbimvaa and
tlbimva operations are detailed in the "ARM Architecture Reference
Manual ARMv7-A" edition, issue "C.c" page B4-1747.
TEST: Booted Beaglebone Black (my current in progress port)
Change-Id: Ie7dfb4adab20dc7eecb1b20aa2ee6355215a1521
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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We always have it, no need to support opting-out.
For PLATFORM_HAS_DRAM_CLEAR there is a dependency of ramstage
located inside CBMEM, which is only true with ARCH_X86.
Change-Id: I5cbf4063c69571db92de2d321c14d30c272e8098
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43014
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Doesn't affect existing x86_32 code.
Tested on qemu using division by zero.
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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No x86 mainboard has a reset.c file.
Change-Id: I167629c7addf485944926d57cf0228606c0f32e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42582
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Refer to section 7.9 Port Connector Information of DSP0134_3.3.0
to add type 8 data, the table of data should be ported according
to platform design and MB silkscreen.
Change-Id: I81e25d27c9c6717750edf1d547e5f4cfb8f1da14
Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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|
In some rare cases it seems that make tries to build
$(objgenerated)/assembly.inc before the build-dirs target has finished,
and so assembly.inc can't be written. Enforce that build-dirs is done
before assembly.inc starts.
BUG=chromium:1098215
BRANCH=none
TEST=none
Change-Id: Ib141ea45a43836cfdde0059523c331fe5286b06d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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variable
If VPD_SMBIOS_VERSION is selected, it would read VPD_RO variable that can
override SMBIOS type 0 version.
One special scenario of using this feature is to assign a BIOS version to
a coreboot image without the need to rebuild from source.
VPD_SMBIOS_VERSION default is n.
Tested=On OCP Delta Lake, dmidecode -t 0 can see the version being updated
from VPD.
Change-Id: Iee62ed900095001ffac225fc629b3f2f52045e30
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: insomniac <insomniac@slackware.it>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
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For type 3, override chassis asset_tag_number with smbios_mainboard_asset_tag()
and add two functions that can override chassis version and serial_number.
For type 4 add smbios_processor_serial_number() to override serial_number.
Tested on OCP Tioga Pass.
Change-Id: I80c6244580a4428fab781d760071c51c7933abee
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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|
Except for whitespace and varying casts the codes were
the same when implemented.
Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.
Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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With RELOCATABLE_RAMSTAGE the backing up of low memory
on S3 resume path was dropped. We forgot some things
behind.
Change-Id: I674f23dade0095e64619af0ae81e23368b1ee471
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The assumption up to this point was that if the system had an x86
processor, verstage would be running on the x86 processor. With running
verstage on the PSP, that assumption no longer holds true, so exclude
pieces of code that cause problems for verstage on the PSP.
As a generalization, remove all-y for CONFIG_ARCH_xx guarded
makefiles.
BUG=b:158124527
TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia7dcfed699ee1c0cd5a5250431c5f05bf6d8b9c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This allows to remove references to CONFIG_DCACHE_RAM entries in
most cache_as_ram.S files. While Kconfig variable names appear
for every stage, linker symbol names will only appear in stages
they are valid in.
Also, linker scripts have LOG2CEIL which comes in handy to enforce
MTRR alignments.
Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30872
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that Picasso uses its own memlayout.ld, always include id.ld in
arch/x86/memlayout.ld.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I04b59c2a273cad0a2e64dbc325c0b09fca254558
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42266
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Now that Picasso uses its own linker script, early_ram.ld from
arch/x86 is unused and hence is dropped as part of this change.
BUG=b:155322763
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ida83d40d005ddab789628a1581389fc487b10d4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows
SoC/mainboard to provide a linker file for the platform. x86 already
provides a default memlayout.ld under src/arch/x86. With this new
Kconfig variable, it is possible for the SoC/mainboard code for x86 to
provide a custom linker file as well.
Makefile.inc is updated for all architectures to use this new Kconfig
variable instead of assuming memlayout.ld files under a certain
path. All non-x86 boards used memlayout.ld under mainboard
directory. However, a lot of these boards were simply including the
memlayout from SoC. So, this change also updates these mainboards and
SoCs to define the Kconfig as required.
BUG=b:155322763
TEST=Verified that abuild with --timeless option results in the same
coreboot.rom image for all boards.
Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ib98483e5d6fcd66fdc72f6157a5bf185fef13016
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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This gets rid of the magic numbers in Kconfig.
Change-Id: Ibee033b6c99e3131bb323f0d86d306dcd82f9b45
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Now that there is a generic solution in mtrr subsystem utilize
the API.
BUG=b:155426691,b:155322763
Change-Id: Ie349d5669808928c7470c99d25c57c784174b4e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41850
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Found using:
diff <(git grep -l '#include <cbfs.h>' -- src/) <(git grep -l 'cbfs_boot_map_optionrom\|cbfs_boot_map_optionrom_revision\|cbfs_boot_locate\|cbfs_boot_map_with_leak\|cbfs_locate_file_in_region\|cbfs_boot_load_file\|cbfs_load_and_decompress\|cbfs_prog_stage_load\|cbfs_boot_region_device' -- src/) |grep '<' |grep -v vendorcode
Also add missing 'include <cbfs.h>' in src/soc/qualcomm/sc7180/qupv3_config.c
Change-Id: Icaecb5b910888f34cddedab7b2f64eaf6d01ad66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41682
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>,
<stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes
each time when <types.h> is included.
Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Builds where RESET_X86_VECTOR is adjusted would create unintentionally
large bootblock files since id section can move far away from .reset
and .text. Some builds segfault or may try to create close to 4 GB
large intermediate build objects.
For cases where build is successful, id section would not reside within
REGION(program) or REGION(bootblock).
A proper fix to always place the ID data at the end of the coreboot.rom
file is left as follow-up work. For now, just place id section below
.reset.
Change-Id: Idf0e4defcde6d5e264d4752cc93f4ffb6749d287
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The sections .rom.* were for romcc and no longer used.
Some romcc comments were left behind when guards were removed.
Change-Id: I060ad7af2f03c67946f9796e625c072b887280c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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After removal of CAR_MIGRATION there are no more reasons
to carry around ENV_STAGE_HAS_BSS_SECTION=n case.
Replace 'MAYBE_STATIC_BSS' with 'static' and remove explicit
zero-initializers.
Change-Id: I14dd9f52da5b06f0116bd97496cf794e5e71bc37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Unused includes found using following commande:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|atol\|strrchr\|skip_atoi\|STRINGIFY' -- src/) |grep -v vendorcode |grep '<'
Change-Id: Ibaeec213b6019dfa9c45e3424b38af0e094d0c51
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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Change-Id: Iad5540e791075270453a136a058823c28647f93a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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This is required to enable VBOOT_STARTS_IN_BOOTBLOCK and
VBOOT_SEPARATE_VERSTAGE for picasso.
BUG=b:147042464
TEST=Boot verstage on picasso
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic3e261a6919a78760d567be9cc684494a5aeab6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I93d0ef6db417904c345fe7b76730bcb70ba25089
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41361
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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unused includes of <stdin.h> found using following commande:
diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l
'int8_t\|uint8_t\|int16_t\|uint16_t\|int32_t\|uint32_t\|int64_t\|
uint64_t\|intptr_t\|uintptr_t\|intmax_t\|uintmax_t\|s8\|u8\|s16\|
u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|UINT8_MAX\|INT16_MIN\
|INT16_MAX\|UINT16_MAX\|INT32_MIN\|INT32_MAX\|UINT32_MAX\|INT64_MIN\
|INT64_MAX\|UINT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|UINTMAX_MAX' -- src/)
|grep '<' |grep -v vendor |grep -vF '.h'
Change-Id: Icb9b54c6abfb18d1e263665981968a4d7cccabeb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41148
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The only caller is contained within the postcar_loader compilation unit.
Therefore, remove postcar_frame_common_mtrrs() from the global symbol
namespace.
Change-Id: I90d308669d13eb2bebf1eca4d47e3f3b4f178714
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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In order to the Kconfigs in the same directory where the corresponding
code lives, this change moves ACPI_BERT to arch/x86/Kconfig and
following configs to acpi/Kconfig:
ACPI_CPU_STRING
ACPI_HAVE_PCAT_8259
ACPI_NO_PCAT_8259
HAVE_ACPI_TABLES
BUG=b:155428745
Change-Id: I289565f38e46bd106ff89685aaf8f57e53d9827a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40932
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split
into multiple CLs. This is change 5/5 which moves the addition of ACPI
table related files from arch/x86/Makefile.inc to acpi/Makefile.inc.
BUG=b:155428745
Change-Id: I8143fd37357aeb0561516450adddc6714d539ada
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 4/5 which gets rid of the placeholder
header files that were added to temporarily include acpi/ header files
from arch/header files.
BUG=b:155428745
Change-Id: If6e8580c3c6433f9239e06a1dc7ba661b3f597e5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 2/5 which moves the contents of
arch/x86/include/arch/acpi*.h files into include/acpi/acpi*.h and
updates the arch header files to include acpi header files. These are
just temporary placeholders and will be removed later in the series.
BUG=b:155428745
Change-Id: I9acb787770b7f09fd2cbd99cb8d0a6499b9c64b3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 1/5 which moves .c files from arch/x86 to
acpi/.
The only acpi files that are still retained under arch/x86 are:
a. acpi_s3.c: This doesn't really deal with ACPI tables. Also, there
are some assumptions in there about SMM which will have to be resolved
if this file needs to be moved to common code.
b. acpi_bert_storage.c/bert_storage.h: This file is currently written
specifically with x86 in mind. So, not moving the file for now.
Motivation for this change: Not all stages on Picasso SoC are targeted
for the same architecture. For example, verstage (if runs before
bootblock) will be targeted for non-x86. This makes it difficult to
add device tree to verstage which would be required to get to SoC
configs from the tree. This is because the device tree on x86
platforms currently contains a lot of devices that require ACPI
related enums and structs (like acpi_gpio, acpi_pld, acpi_dp and so
on). Hence, this change removes all ACPI table support out of
arch/x86.
BUG=b:155428745
Change-Id: Icc6b793c52c86483a8c52e0555619e36869a869e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This change makes power_res_dev_states[] to be static const * const as
complained by Jenkins.
BUG=b:155428745
Change-Id: Ice2fff6ab3bcd72a059bc905b7462a681f2e6aaf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change adds a helper function cpu_get_lapic_addr() that returns
LOCAL_APIC_ADDR for x86. It also adds a weak default implementation
which returns 0 if platform does not support LAPIC. This is being
done in preparation to move all ACPI table support in coreboot out of
arch/x86.
BUG=b:155428745
Change-Id: I4d9c50ee46804164712aaa22be1b434f800871ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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An array of 64bit integers is passed to acpi_dp_add_integer_array() but
it is not const so can't take a const array without a compiler error.
The function does not modify the array so it can be made const without
breaking anything and allowing a const array to be passed in the future.
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I98ecdaef5ddfa2026390e2812f5ea841ee51f073
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40882
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The generic container HID is defined in ACPI specification as PNP0A05.
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I3632e77533a47f22b92259b469b03e63f51687e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Currently if a child table is created and added to a property list
without adding any properties to that child it will generate an
empty package. For example:
struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
struct acpi_dp *prop = acpi_dp_new_table("PROP");
acpi_dp_add_child(dsd, "dsd-prop", prop);
acpi_dp_write(dsd);
Results in an empty PROP package:
Name (_DSD, Package (2)
{
ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b")
Package (1) {
Package (2) {
"dsd-prop",
"PROP"
}
}
}
Name (PROP, Package (0)
{
}
Empty packages don't seem to be explicitly forbidden, but they don't
serve a purpose with device properties. Instead, if packages without
any properties or children are skipped then this empty package is not
written and the added child property can refer to another property that
is already defined.
This allows creating property references to existing tables, which can
save duplication and namespace collision issues with nested properties.
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I9fee2ceb8a4496b90c7210533eee8c2b186cdfff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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acpigen_write_field() does not need to modify the fieldlist
parameter. Thus, this change makes this parameter as const.
Change-Id: I94688913cee8948f42ae5e184f2d24264876648d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40784
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change adds the following acpigen helpers:
a. acpigen_write_store_op_to_namestr: This generates ACPI code for
storing an ACPI OP to name string
b. acpigen_write_if_lequal_namestr_int: This generates ACPI code for
checking if operand1 and operand2 are equal where operand1 is
namestring and operand2 is an integer.
Change-Id: I84c158361c0725c2927f06be35391e61f627a453
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40783
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add support for devices with the reset vector pointing into DRAM. This
is a specific implementation that assumes a paradigm of AMD Family 17h
(a.k.a. "Zen"). Until the first ljmpl for protected mode, the core's
state appears to software like other designs, and then the actual
physical addressing becomes recognizable.
These systems cannot implement cache-as-RAM as in more traditional
x86 products. Therefore instead of reusing CAR names and variables,
a substitute called "earlyram" is introduced. This change makes
adjustments to CAR-aware files accordingly.
Enable NO_XIP_EARLY_STAGES. The first stage is already in DRAM, and
running subsequent stages as XIP in the boot device would reduce
performance.
Finally, add a new early_ram.ld linker file. Because all stages run in
DRAM, they can be linked with their .data and .bss as normal, i.e. they
don't need to rely on storage available only at a fixed location like
CAR systems. The primary purpose of the early_ram.ld is to provide
consistent locations for PRERAM_CBMEM_CONSOLE, TIMESTAMP regions, etc.
across stages until cbmem is brought online.
BUG=b:147042464
TEST=Build for trembyle, and boot to ramstage.
$ objdump -h cbfs/fallback/bootblock.debug
Idx ,Name ,Size ,VMA ,LMA ,File off Algn
0 ,.text ,000074d0 ,08076000 ,08076000 ,00001000 2**12
1 ,.data ,00000038 ,0807d4d0 ,0807d4d0 ,000084d0 2**2
2 ,.bss ,00000048 ,0807d508 ,0807d508 ,00008508 2**2
3 ,.stack ,00000800 ,0807daf0 ,0807daf0 ,00000000 2**0
4 ,.persistent ,00001cfa ,0807e2f0 ,0807e2f0 ,00000000 2**0
5 ,.reset ,00000010 ,0807fff0 ,0807fff0 ,0000aff0 2**0
6 ,.debug_info ,0002659c ,00000000 ,00000000 ,0000b000 2**0
7 ,.debug_abbrev ,000074a2 ,00000000 ,00000000 ,0003159c 2**0
8 ,.debug_aranges,00000dd0 ,00000000 ,00000000 ,00038a40 2**3
9 ,.debug_line ,0000ad65 ,00000000 ,00000000 ,00039810 2**0
10 ,.debug_str ,00009655 ,00000000 ,00000000 ,00044575 2**0
11 ,.debug_loc ,0000b7ce ,00000000 ,00000000 ,0004dbca 2**0
12 ,.debug_ranges ,000029c0 ,00000000 ,00000000 ,00059398 2**3
Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35035
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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.acpi_fill_ssdt() does not need to modify the device structure. This
change makes the struct device * parameter to acpi_fill_ssdt() as
const.
Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
