coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-02-20	arch/riscv: Align trap_entry to 4 bytes, as required by spec	Jonathan Neuschäfer
	The RISC-V Privileged Architecture spec 1.10 requires that the address part of mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should be zero for now. Add the necessary alignment directive before trap_entry. Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02	arch/riscv: Remove supervisor_trap_entry	Jonathan Neuschäfer
	coreboot only maintains a single trap entry, because it only runs in machine mode. Change-Id: I7324d9c8897d5c4e9d4784e7bc2a055890eab698 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02	arch/riscv: Return from trap_handler instead of jumping out	Jonathan Neuschäfer
	Change-Id: I8dbed5dbe377d3a02e58a3bc16a1ee112b28bea9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-12-02	arch/riscv: Unify trap return	Jonathan Neuschäfer
	Change-Id: I9de0c92b3f925e8f4db00d7281222a07db68b2ae Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07	arch/riscv: Use a separate trap stack	Jonathan Neuschäfer
	This is the lazy solution, as explained in the comment, but it works for now. Change-Id: I46e18b6d633280d6409e42462500fbe7c6823b4d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07	arch/riscv: Drop mret workaround	Jonathan Neuschäfer
	Our toolchain can compile mret now, and once the encoding changes, we'll have to adjust the code anyway. Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-01-16	riscv: get SBI calls to work	Ronald G. Minnich
	SBI calls, as it turned out, were never right. They did not set the stack correctly on traps. They were not correctly setting the MIP instead of the SIP (although this was not really well documented). On Harvey, we were trying to avoid using them, and due to a bug in SPIKE, our avoidance worked. Once SPIKE was fixed, our avoidance broke. This set of changes is tested and working with Harvey which, for the first time, is making SBI calls. It's not pretty and we're going to want to rework trap_util.S in coming days. Change-Id: Ibef530adcc58d33e2c44ff758e0b7d2acbdc5e99 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18097 Tested-by: build bot (Jenkins)
2016-11-02	riscv: Add a bandaid for the new toolchain	Ronald G. Minnich
	After I did a new toolchain build, I found the the mhartid register value is wrong for Spike. The docs seem to agree with Spike, not the code the toolchain produces? Until such time as the bitstreams and toolchain can find a way to agree, just hardcode it. We've been playing this game for two years now so this is hardly a new approach. This is intentionally ugly because we really need the toolchains and emulators and bitstreams to sync up, and that's not happening yet. Lowrisc allegedly implements the v1.9 spec but it's PTEs are clearly 1.7. Once it all settles down we can just use constants supplied by the toolchain. I hope the syncup will have happened by the workshop in November. This gets spike running again. Change-Id: If259bcb6b6320ef01ed29a20ce3d2dcfd0bc7326 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17183 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-08-15	arch/riscv: Set the stack pointer upon trap entry	Jonathan Neuschäfer
	Change-Id: I52fae62bc6cf775179963720fbcfaa9e07f6a717 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16017 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-18	arch/riscv: Change all eret instructions to .word 0x30200073 (mret)	Jonathan Neuschäfer
	Using the opcode directly is necessary for the transition to the GCC 6.1.0 based toolchain, because the old toolchain only supports eret and the new toolchain only supports mret. Change-Id: I17e14d4793ae5259f7ce3ce0211cbb27305506cc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15290 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12	arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constant	Jonathan Neuschäfer
	Change-Id: I9759771fa6fc708d7d97509c5f5e0cefb8ab4c96 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14962 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
	It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-15	riscv-trap-handling: Add functionality, prevent stack corruption	Thaminda Edirisooriya
	Trap handling code was bugged in that it loaded in the wrong stack pointer, overwriting the space the processor uses to talk to its host for doing device requests. Fix this issue, as well as add support for handling misaligned loads the same way we handle misaligned stores. Change-Id: I68ba3a114b7167b3212bb0bed181a7595f0b97d8 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11620 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-10	riscv-trap-handling: Add implementation for trap calls in riscv	Thaminda Edirisooriya
	RISCV requires the bios/bootloader to set up an interface by which it can get information about memory, talk to host devices, etc. Put implementation for spike in src/mainboard/emulation/spike-riscv/spike_util.c, and src/arch/riscv/trap_handler.c Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11368 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-08-26	riscv-trap-handling: Add preliminary trap handling for riscv	Thaminda Edirisooriya
	RISCV requires a trap handler at the machine stage to deal with misaligned loads/stores, as well as to deal with calls that a linux payload will make in its setup. Put required assembly for jumping into and out of a trap here to be set up by the bootblock in a later commit. Change-Id: Ibf6b18e477aaa1c415a31dbeffa50a2470a7ab2e Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11367 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)