diff options
| author | Thaminda Edirisooriya <thaminda@google.com> | 2015-08-26 14:54:31 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-09-10 17:26:38 +0000 |
| commit | 95ba4c87f5f4802e2afaeae38003db5e7235864a (patch) | |
| tree | 5e1c146e873afc58695ee22a056f5546b6cc8bed /src/arch/riscv/trap_util.S | |
| parent | b094583c6fd9d330be28ed6feb1c1140de07ff37 (diff) | |
riscv-trap-handling: Add implementation for trap calls in riscv
RISCV requires the bios/bootloader to set up an interface by which it
can get information about memory, talk to host devices, etc. Put
implementation for spike in
src/mainboard/emulation/spike-riscv/spike_util.c, and
src/arch/riscv/trap_handler.c
Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11368
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/trap_util.S')
| -rw-r--r-- | src/arch/riscv/trap_util.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 08061eb537..9701aaf1f6 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -121,7 +121,7 @@ supervisor_trap_entry: trap_entry: csrw mscratch, sp 1:addi sp,sp,-320 - save_tf_ + save_tf move a0,sp jal trap_handler .global supervisor_call_return |