Age | Commit message (Expand) | Author |
---|---|---|
2018-10-06 | arch/riscv: Update comment about mstatus initialization | Jonathan Neuschäfer |
2018-09-05 | riscv: add entry assembly file for RAMSTAGE | Xiang Wang |
![]() |
index : coreboot.git | |
my copy of coreboot | gitea |
aboutsummaryrefslogtreecommitdiff |
Age | Commit message (Expand) | Author |
---|---|---|
2018-10-06 | arch/riscv: Update comment about mstatus initialization | Jonathan Neuschäfer |
2018-09-05 | riscv: add entry assembly file for RAMSTAGE | Xiang Wang |