| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-02-02 | riscv: Simplify payload handling | Xiang Wang |
| 2018-02-20 | arch/riscv: Pass the bootrom-provided FDT to the payload | Jonathan Neuschäfer |
| 2017-11-07 | arch/riscv: Drop mret workaround | Jonathan Neuschäfer |
| 2016-11-13 | riscv: change payload() to pass the config string pointer as arg0 | Ronald G. Minnich |
| 2016-10-24 | RISCV: Clean up the common architectural code | Ronald G. Minnich |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |