| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-06-23 | riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths | Xiang Wang |
| 2019-02-13 | riscv: Add initial support for 32bit boards | Philipp Hug |
| 2019-02-02 | riscv: Simplify payload handling | Xiang Wang |
| 2018-11-05 | riscv: add support smp_pause / smp_resume | Xiang Wang |
| 2018-09-10 | riscv: update mtime initialization | Xiang Wang |
| 2018-07-12 | riscv: add include/arch/smp/ directory | Xiang Wang |
| 2017-12-02 | arch/riscv: Remove the current SBI implementation | Jonathan Neuschäfer |
| 2017-07-25 | src/arch: Fix checkpatch warning: no spaces at the start of a line | Martin Roth |
| 2017-02-20 | riscv: Suppress invalid coverity errors | Martin Roth |
| 2017-01-16 | riscv: Move mcall numbers to mcall.h, adjust their names | Jonathan Neuschäfer |
| 2017-01-16 | riscv: get SBI calls to work | Ronald G. Minnich |
| 2016-11-07 | riscv: Unify SBI call implementations under arch/riscv/ | Jonathan Neuschäfer |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |