aboutsummaryrefslogtreecommitdiff
path: root/src/arch/armv7/lib
AgeCommit message (Collapse)Author
2013-07-10ARM: Fix up page table/cachability management.Gabe Black
When modifying the page tables, use writel to ensure the writes happen, flush the page tables themselves to ensure they're visible to the MMU if it doesn't look at the caches, and invalidate the right TLB entries. The first two changes are probably safer but may not be strictly necessary. The third change is necessary because we were invalidating the TLB using i which was in megabytes but using an instruction that expects an address in bytes. One symptom of this problem was that the framebuffer, which was supposed to be marked uncacheable, was only being partially updated since some of the updates were still in the cache. With this change the graphics show up correctly. Change-Id: I5475df29690371459b0d37a304eebc62f81dd76b Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3653 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARM: Fix the way the space for the page tables is allocated.Gabe Black
The page tables need to be aligned to a 16KB boundary and are 16KB in size. The CBMEM allocator only guarantees 512 byte alignment, so to make sure things are where they're supposed to be, the code was allocating extra space and then adjusting the pointer upwards. Unfortunately, it was adding the size of the table to the pointer first, then aligning it. Since it allocated twice the space of the table, this had the effect of moving past the first table size region of bytes, and then aligning upwards, pushing the end of the table out of the space allocated for it. You can get away with this if you push things you don't care about off the end, and it happened to be the case that we were allocating a color map we weren't using at the start of the next part of cbmem. Change-Id: I6b196fc573801b02f27f2e667acbf06163266651 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3651 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARMv7: De-uboot-ify Exynos5250 codeStefan Reinauer
When starting the Exynos5250 port, a lot of unneeded u-boot code was imported. This is an attempt to get rid of a lot of unneeded code before the port is used as a basis for further ARM ports. There is a lot more that can be done, including cleaning up the 5250's Kconfig file. Change-Id: I2d88676c436eea4b21bcb62f40018af9fabb3016 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3642 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-01armv7: invalidate TLB entries as they are added/modifiedDavid Hendricks
The old approach was to invalidate the entire TLB every time we set up a table entry. This worked because we didn't turn the MMU on until after we had set everything up. This patch uses the TLBIMVAA wrapper to invalidate each entry as it's added/modified. Change-Id: I27654a543a2015574d910e15d48b3d3845fdb6d1 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3166 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-01ARMV7: add a function to disable MMU entriesRonald G. Minnich
It is useful to be able to lock out certain address ranges, NULL being the most important example. void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) will allow us to lock out selected virtual addresses on MiB boundaries. As in other ARM mmu functions, the addresses and quantities are in units of MiB. Change-Id: If516ce955ee2d12c5a409f25acbb5a4b424f699b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3160 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-04-17armv7/exynos5250: Deprecate sdelay in favor of udelayDavid Hendricks
This gets rid of the clock-tick based sdelay in favor of udelay(). udelay() is more consistent and easier to work with, and this allows us to carry one less variation of timers (and headers and sources...). Every 1 unit in the sdelay() argument was assumed to cause a delay of 2 clock ticks (@1.7GHz). So the conversion factor is roughly: sdelay(N) = udelay(((N * 2) / 1.7 * 10^9) * 10^6) = udelay((N * 2) / (1.7 * 10^3)) The sdelay() periods used were: sdelay(100) --> udelay(1) sdelay(0x10000) --> udelay(78) (rounded up to udelay(100)) There was one instance of sdelay(10000), which looked like sort of a typo since sdelay(0x10000) was used elsewhere. sdelay(10000) should approximate to about 12us, so we'll stick with that for now and leave a note. Change-Id: I5e7407865ceafa701eea1d613bbe50cf4734f33e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3079 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-13Exynos5250: add a microsecond timerRonald G. Minnich
Add a microsecond timer, its declaration, the function to start it, and its usage. To start it, one calls timer_start(). From that point on, one can call timer_us() to find microseconds since the timer was started. We show its use in the bootblock. You want it started very early. Finally, the delay.h change having been (ironically) delayed, we create time.h and have it hold one declaration, for the timer_us() and timer_start() prototype. We feel that these two functions should become the hardware specific functions, allowing us to finally move udelay() into src/lib where it belongs. Change-Id: I19cbc2bb0089a3de88cfb94276266af38b9363c5 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3073 Tested-by: build bot (Jenkins)
2013-03-29armv7: remove loop from dcache_mmu_disable()David Hendricks
dcache_mmu_disable() no longer needs to have its own iterative loop to select each cache level of cache since dcache_clean_invalidate_all() does that now. Change-Id: I5ca273f98943981b943c1c1622f4574d7133fb50 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2967 Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
2013-03-29armv7: update sync barrier usage in dcache_op_set_way()David Hendricks
This moves the dsb() before the loop to sync any outstanding memory accesses, and adds an isb() after the loop to ensure all outstanding instructions are completed. Change-Id: I1a11b39f104ae780370cfd2db3badcf4e91dc017 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2929 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29armv7: set cache level explicitly for dcache/unified cache caseDavid Hendricks
This adds a missing CSSELR write in the case of a dcache or unified cache being invalidated by armv7_invalidate_caches(), ensuring that all levels of dcache/unified cache are invalidated as expected when the function is called. Change-Id: Ie90184bf8a8181afa3afe0786897455b30b7f022 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2947 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-03-29armv7: invalidate TLB after changing translation table entriesDavid Hendricks
This adds a call to tlb_invalidate_all() after configuring a range of memory. Change-Id: I558402e7e54b6bf9e0b013f153d9b84c0873a6cf Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2946 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-03-29armv7: iterate thru all levels when doing dcache opsDavid Hendricks
This makes dcache maintenance functions operate on all levels of cache instead of just the current one. Change-Id: I2708fc7ba6da6740dbdfd733d937e7c943012d62 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2945 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-03-29armv7: use stdint.h in cache and MMU filesDavid Hendricks
This makes it easier to copy + paste code into libpayload since libpayload since both coreboot and libpayload have stdint.h and it defines the types needed. Change-Id: Ifa55f04a9bdddd17bc1a2679321a6744c75f25a8 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2944 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-28armv7: clean+invalidate all cache levels when disabling MMUDavid Hendricks
This iterates thru all cache levels and cleans + invalidates all data and unified caches before disabling dcache and MMU. Change-Id: I8a671b4c90d7b88b8d0a95947bfa17f912cebaa2 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2930 Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
2013-03-28armv7: cosmetic changes to dcache_op_mva()David Hendricks
This is just a cosmetic change to dcache_op_mva() to (hopefully) make it a easier to follow and more difficult to screw up. Change-Id: Ia348b2d58f2f2bf5c3cafabcfba06bc411937dba Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2927 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-28armv7: fix a bad variable assignmentDavid Hendricks
'<' was used when '<<' is needed. Oops! Change-Id: I8451f76888e86219df16b50739cd2c8db80dcb14 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2941 Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
2013-03-28armv7: pass incremented value to dccimvacDavid Hendricks
This passes the correct value into dccimvac. Change-Id: I6098440ea48a9b6429380d5913fce6d36e3afb41 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2926 Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
2013-03-26armv7: fixes for dcache_op_by_mva()David Hendricks
This fixes a couple issues with dcache_op_by_mva(): - Add missing data and instruction sync barriers. - Removes unneded -1 from loop terminating condition. Change-Id: I098388614397c1e53079c017d56b1cf3ef273676 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2913 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-26armv7: add new dcache and MMU setup functionsDavid Hendricks
This adds new MMU setup code. Most notably, this version uses cbmem_add() to determine the translation table base address, which in turn is necessary to ensure payloads which wipe memory can tell which regions to wipe out. TODOs: - Finish cleaning up references to old cache/MMU stuff - Add L2 setup (from exynos_cache.c) - Set up ranges dynamically rather than in ramstage's main(). Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2877 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21armv7: add function for dcache_clean_by_mva()David Hendricks
This adds a function for using the DCCMVAC instruction (dcache clean by MVA at point of coherency (main memory)). We already have the inline defined, it's just not used by anything. Change-Id: Ia0641566a8881335bed8da2963e1db8321d74267 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2871 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-21armv7: add a helper function for dcache ops by MVADavid Hendricks
This adds a helper function for dcache ops by MVA which will perform the specified operation on a given memory range. This will make it more trivial to add other data cache maintenance routines. Change-Id: I01d746d5fd2f4138257ca9cab9e9d738e73f8633 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2870 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-21armv7: cosmetic changes to new cache codeDavid Hendricks
This clarifies and/or fixes formatting of some comments and alphabetizes some function prototypes and inlines. It also corrects references to "modified virtual address" (MVA). Change-Id: Ibcdda4febf915cc4a1996a5bbb4ffecbcb50a324 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2869 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-21armv7: move armv7_invalidate_caches() to cache.cDavid Hendricks
This just moves cache maintenance stuff from the armv7 bootblock code to cache.c Change-Id: I0b3ab58a1d8a3fe3d9568e02e156a36b6f33ca0b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2867 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-19armv7/exynos/snow: new cache maintenance APIDavid Hendricks
This adds a new API for cache maintenance operations. The idea is to be more explicit about operations that are going on so it's easier to manage branch predictor, cache, and TLB cleans and invalidations. Also, this adds some operations that were missing but required early on, such as branch predictor invalidation. Instruction and sync barriers were wrong earlier as well since the imported API assumed we compield with -march=armv5 (which we don't) and was missing wrappers for the native ARMv7 ISB/DSB/DMB instructions. For now, this is a start and it gives us something we can easily use in libpayload for doing things like cleaning and invalidating dcache when doing DMA transfers. TODO: - Set cache policy explicitly before re-enabling. Right now it's left at default. - Finish deprecating old cache maintenance API. - We do an extra icache/dcache flush when going from bootblock to romstage. Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2729 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-08Eliminate do_div().David Hendricks
This eliminates the use of do_div() in favor of using libgcc functions. This was tested by building and booting on Google Snow (ARMv7) and Qemu (x86). printk()s which use division in vtxprintf() look good. Change-Id: Icad001d84a3c05bfbf77098f3d644816280b4a4d Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2606 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-07Revert "ARMv7: Simplify div64"David Hendricks
This reverts commit 1cd616082100f47dc2d6d73669c6aa2e5eb039ad Division bites us again. I don't know how or why, but printk() seems to break (again) with this patch. I'm surprised we didn't encounter problems earlier on... Change-Id: I81cb9f20879f5eb73a76e1af47b96a68d1e81dc8 TODO: Find a better solution for div64. This one is too painful, but seems necessary for now (and sort-of works with our vtxprintf hack). Reviewed-on: http://review.coreboot.org/2600 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-25ARMv7: Simplify div64Stefan Reinauer
We don't need the overly complex optimized version, since we're only doing this in very few non-critical places. Also, add the div* files to the bootblock, they're needed if we do printk. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I83bd766d4b03b488326ade1c13b7c364a7119e7b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2508 Tested-by: build bot (Jenkins)
2013-02-20Whitespace: Replace tab character in license text with two spacesPaul Menzel
For whatever reason tabs got inserted in the license header text. Remove one occurrence of that with the following command [1]. $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[ ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,' [1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2460 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2013-02-20ARMV7: minor tweaks to inter-stage calling and payload handling.Ronald G. Minnich
Payloads, by design, can return. There's lots of mechanism in the payload code to support it, and the chooser payload relies on it. Hence, we should not mark the function call in exit_stage as noreturn. Not all ARM have unified caches, and it's not always easy to tell what to do. So we are very paranoid. Before we call between stages, we should carefully flush the dcache to memory and invalidate the icache. This may be more than is necessary on all architectures but it doesn't really hurt for the most part. So compile cache management code into all stages, and call the flush dcache/invalidate icache from all stages. Change-Id: Ib9cc625c4dfd2d7d4b3c69a74686cc655a9d6484 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2462 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-15ARMv7: Drop u-boot type remainsStefan Reinauer
Just a mechanical cleanup. Change-Id: I0815625e629ab0b7ae6c948144085f1bd8cabfb5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2408 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-15ARMv7: straighten out reset codeStefan Reinauer
We don't need three different implementations. Change-Id: Ie7b5fa90794676ea38838454a33e8e9188428eb7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2406 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-15ARMv7: Drop sr32, and wait_on_valueStefan Reinauer
They're unused. Also drop some unused defines in system.h Change-Id: Ia5afc3a676a4a94787041430f05d08f333033c73 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2404 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-02-15ARMv7: Fix include file names in memset & memcpyStefan Reinauer
We don't have asm/ Change-Id: I7f80f47e9d7f457b7a5a64603c59b14d3b536a8c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2403 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-13armv7/exynos: remove some stale files leftover from initial importDavid Hendricks
This removes some files leftover from the initial port. Some are leftover from U-Boot and some were leftover from the skeleton code derived from x86. There's a bit more that we'll get in another sweep. Change-Id: I325793ecb902b3b9430dcf531714ce025d201de6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2380 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-13armv7: use start and size parameters in mmu_setup()David Hendricks
mmu_setup() was originally written in U-Boot to utilize board-specific global data. Since we're trying to avoid that, we added start and size parameters so that board-specific info can be passed in via mainboard code. Let's start using it that way. Change-Id: I7d7de0e42bd918c9f9f0c177acaf56c110bf8353 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2378 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-10armv7/exynos5250: place .id between .start and bootblock mainDavid Hendricks
This places the .id section toward the lower region of the coreboot image, before the bootblock. It's easier for humans to find by dumping the image and it also eliminates ID_SECTION_OFFSET which is currently the upper bound on our image size. Change-Id: I7d737b901dac659ddf9aa437cee5dc32f1080546 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2345 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-08armv7: Use same console initialization procedure for all ARM stagesHung-Te Lin
Use same console initialization procedure for all ARM stages (bootblock, romstage, and ramstage): #include <console/console.h> ... console_init() ... printk(level, format, ...) Verified to boot on armv7/snow with console messages in all stages. Change-Id: Idd689219035e67450ea133838a2ca02f8d74557e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2301 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-08console: Revise serial console configuration names.Hung-Te Lin
The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-07armv7: Clean up arm/snow bootblock build process.Hung-Te Lin
Remove duplicated / testing code and share more driver for bootblock, romstage and ramstage. The __PRE_RAM__ is now also defined in bootblock build stage, since bootblock is executed before RAM is initialized. Change-Id: I4f5469b1545631eee1cf9f2f5df93cbe3a58268b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2282 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-06armv7: Clean up: remove deprecated SPL.Hung-Te Lin
"SPL" from U-Boot is deprecated by bootblock in coreboot/arm, so we don't need it anymore. Change-Id: Id16877075d0b870839a10160073ad70777a2af0a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2297 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-06armv7: Clean up: replace hang() by hlt().Hung-Te Lin
hang() is the legacy function from U-boot and should be replaced by hlt() in coreboot. Change-Id: I0f390b1b6f9ff71487ea36cf16c462724b66d8ca Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2298 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-04exynos/snow: partial clean-up of snow bootblock using build classDavid Hendricks
This removes some duplicate code from Snow's mainboard bootblock by utilizing the bootblock build class. Change-Id: I153247370a8c5127260082dcdca3ebdc5e104fb8 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2270 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-03armv7: Add 'bootblock' build class.Hung-Te Lin
For ARM platform, the bootblock may need more C source files to initialize UART / SPI for loading romstage. To preventing making complex and implicit dependency by using #include inside bootblock.c, we should add a new build class "bootblock". Also #ifdef __BOOT_BLOCK__ can be used to detect if the source is being compiled for boot block. For x86, the bootblock is limited to fewer assembly files so it's not using this class. (Some files shared by x86 and arm in top level or lib are also changed but nothing should be changed in x86 build process.) Change-Id: Ia81bccc366d2082397d133d9245f7ecb33b8bc8b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2252 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-01armv7: unify stage hand-off routinesDavid Hendricks
This replaces the current stage-specific exit/entry functions with generic versions. Now all stages compile with stage_entry(), which is placed at .text.stage_entry.armv7, and stage_exit(). Snow's ramstage files are also updated to avoid build breakage. Change-Id: I953a2c4b8121bd4b66c3362557997a9ca3aa53b0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2254 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-01-30armv7: don't hang on divide by zeroRonald G. Minnich
People make mistakes. Hanging the box is not a good reason to kill the firmware, esp. since this is probably happening in a printk. The only issue with the recursive call to printk is that we may deadlock if we have locked something. But we can at least try. Hanging is certainly not what we want ... Change-Id: Ib3bc87bc395ae89e115cf6d042f4167856422ca1 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2233 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-01-29armv7: Clean up the mmu setup a bitRonald G. Minnich
The previous incarnation did not use all of mmu_setup, which meant we did not carefully disable things before (possibly) changing them. This code is tested and works, and it's a bit of a simplification. Change-Id: I0560f9b8e25f31cd90e34304d6ec987fc5c87699 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2204 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2013-01-29armv7: nuke global_data.h and remove some references to gd structDavid Hendricks
This begins to remove references to global data which u-boot used. There are still many commented out references to gd-> and bd-> which we'll fix once we're happy with the replacements. Change-Id: Ie1b40a997e28a118f8f3ad96a2f9a2462d32fbe3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2210 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-29armv7: Clean out weak symbols and unnecessary #ifdef's in cache filesDavid Hendricks
This just removes unused code. If for some reason we don't want to initialize cache, then the CPU or mainboard specific init routines don't need to call these. Change-Id: Ieb7393b6cbc103e490753da4ed27114156466ded Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2209 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-01-19armv7/snow: get to romstageDavid Hendricks
This patch does a few things to get us into romstage: - Add romstage as a stage (a later patch adds it as a binary, which is probably wrong). The Makefile magic is complex enough that we let it build the XIP file for now, but we no longer use it. - Replace findstage with loadstage. Loadstage will find a stage, load the code to memory, and zero the remaining part of memory. Now we can link the romstage to go anywhere! - Eliminate magic offsets from code/ldscripts and centralize Kconfig variables in src/cpu/samsung/exynos5250/Kconfig. - Tidy up code and serial output Change-Id: Iae4d2f9e7f429cb1df15d49daf9a08b88d75d79d Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2174 Tested-by: build bot (Jenkins)
2013-01-18Snow bootblock (bloated/debug version)David Hendricks
This is the bloated Snow bootblock which includes: - SPI driver - UART, including requisite I2C, Maxim PMIC, and clock config code. - Adjustments for magic offsets (id section, stack pointer address) This is just a temporary solution until we have romstage loading. Once that happens, we'll rip out all but the code necessary for copying SPI ROM content into SRAM. Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2170 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-17ARM bootblock approachDavid Hendricks
This lays out the groundwork for using a proper bootblock on ARM. Currently we bypass the bootblock entirely and go straight to romstage. However we want to utilize CBFS to maximize flexibility of placing code without relying on a lot of magic numbers which will break depending on the SoC in use. Change-Id: I9cc2a8191d2db38b27b6363ba673e5a360de9684 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2118 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-16armv7: delete unneeded ptrace.hStefan Reinauer
... and delete traces in source files. Change-Id: Ie0f70a479f1eadadc654a41fa3c426d1d4ac2f2b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2152 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04ARMv7: drop libgcc copyStefan Reinauer
We accidently checked in some files from libgcc as well as a Makefile from u-boot and a duplicate implementation of div0. Drop all those files to reduce the confusion. Change-Id: I8ff6eabbced6f663813f8cc55f19c81839d03477 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2102 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08WIP: Initial ARMv7 architecture implementation in corebootStefan Reinauer
The first ARMv7 CPU we're going to support is the Exynos 5250 used in the Google Snow ChromeBook. Change-Id: I4de8433bbc6202eb8fef2556a11186a3376d411b Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2004 Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-10 16:33:19 +0000