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authorDavid Hendricks <dhendrix@chromium.org>2013-03-28 18:26:03 -0700
committerDavid Hendricks <dhendrix@chromium.org>2013-03-29 18:15:13 +0100
commit7b19f669025a9f1dfc32035d7c93231e7a59c456 (patch)
tree954c990305c681f1474e075b0db41e26f365f0b8 /src/arch/armv7/lib
parent8234874fbc10d71f620a2814a1faaed3b097db6c (diff)
armv7: iterate thru all levels when doing dcache ops
This makes dcache maintenance functions operate on all levels of cache instead of just the current one. Change-Id: I2708fc7ba6da6740dbdfd733d937e7c943012d62 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2945 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/armv7/lib')
-rw-r--r--src/arch/armv7/lib/cache.c29
1 files changed, 27 insertions, 2 deletions
diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c
index 8709daf1ee..da03a81fd8 100644
--- a/src/arch/armv7/lib/cache.c
+++ b/src/arch/armv7/lib/cache.c
@@ -148,14 +148,39 @@ static void dcache_op_set_way(enum dcache_op op)
dsb();
}
+static void dcache_foreach(enum dcache_op op)
+{
+ uint32_t clidr;
+ int level;
+
+ clidr = read_clidr();
+ for (level = 0; level < 7; level++) {
+ unsigned int ctype = (clidr >> (level * 3)) & 0x7;
+ uint32_t csselr;
+
+ switch(ctype) {
+ case 0x2:
+ case 0x3:
+ case 0x4:
+ csselr = level << 1;
+ write_csselr(csselr);
+ dcache_op_set_way(op);
+ break;
+ default:
+ /* no cache, icache only, or reserved */
+ break;
+ }
+ }
+}
+
void dcache_clean_invalidate_all(void)
{
- dcache_op_set_way(OP_DCCISW);
+ dcache_foreach(OP_DCCISW);
}
void dcache_invalidate_all(void)
{
- dcache_op_set_way(OP_DCISW);
+ dcache_foreach(OP_DCISW);
}
static unsigned int line_bytes(void)