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2019-10-03libpayload: refactor fetching cbmem pointersPatrick Georgi
There's a recurring pattern of reading cbtable entries that point into cbmem entries. Move that pattern into its own function. Coccinelle patch used for this: @@ identifier T, T2; expression TARGET; @@ -struct cb_cbmem_tab *const T2 = (struct cb_cbmem_tab *)T; -TARGET = phys_to_virt(T2->cbmem_tab); +TARGET = get_cbmem_ptr(T); Change-Id: I7bd4a7ad8baeeaebf0fa7d4b4de6dbc719bc781f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-05libpayload: Align main() data typesPatrick Georgi
One of many steps to compile with -Wconversion, as unsigned int and int aren't the same thing. BUG=b:111443775 BRANCH=none TEST=make junit.xml shows fewer warnings with -Wconversion enabled Change-Id: I9673ca70da32a1e5117b27fa89167e03379af9c1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-07payloads: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find payloads/ -type f | \ xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I883b03b189f59b5d998a09a2596b0391a2d5cf33 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-04libpayload/x86/exception: Add ability to ignore unknown interruptsRaul E Rangel
This will make enabling the APIC safer by ignoring unknown interrupts and not halting the system. Once all interrupt sources have been found and handled DIE_ON_UNKNOWN_INTERRUPT can be set if desired. BUG=b:116777191 TEST=Booted grunt, halted the kernel, and pushed the power button while in S5. Verified that depthcharge logged the unknown exception. APIC Init Started APIC Configured Ignoring interrupt vector 39 Change-Id: If4ed566ec284d69786c369f37e4e331d7f892c74 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04libpayload/x86/exception.c: Remove exception_install_hookRaul E Rangel
Not used by x86 code anymore. BUG=b:116777191 TEST=Validated that depthcharge can be built. Change-Id: I25ad3903989a5433ce73d657cfdb93dd1f34f7b5 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04libpayload/apic: Register a spurious interrupt vectorRaul E Rangel
We should have a spurious interrupt vector just incase we get one. The handler doesn't need to do anything. BUG=b:116777191 TEST=Booted depthcharge on grunt and inspected the register. I can't generate a spurious interrupt, so I can't validate that the handler gets called. Change-Id: I9e49e617f4375eb5eb00d0715c1902f77e2bf284 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04libpayload/apic: Only ACK interrupts triggered by the APICRaul E Rangel
Only set end of interrupt (EOI) when the APIC In-Service vector matches the interrupt vector. This makes it so we don't EOI a non APIC interrupt. BUG=b:116777191 TEST=Booted grunt with APIC enabled and verified depthcharge still works. Change-Id: I00bd1e7a0fcf2fc004feadc40d22ebfefe68b384 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-28src/*: normalize Google copyright headersPatrick Georgi
As per internal discussion, there's no "ChromiumOS Authors" that's meaningful outside the Chromium OS project, so change everything to the contemporary "Google LLC." While at it, also ensure consistency in the LLC variants (exactly one trailing period). "Google Inc" does not need to be touched, so leave them alone. Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2018-09-12libpayload/x86/delay: Make arch_ndelay call apic_delay if delay is longRaul E Rangel
This reduces power consumption on grunt by over 3W when sitting at the depthcharge recovery screen. BUG=b:109749762 TEST=Booted grunt in the recovery screen and made sure it continued to work. Change-Id: Id079c099ee4cf6a07724241af4400063f4551668 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28245 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Julius Werner <jwerner@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12libpayload/x86/delay: Add an x86 arch_ndelayRaul E Rangel
This method has a pause instruction to help the CPU relax a little bit. Measuring grunt it saves about 80mW. BUG=b:109749762 TEST=Made sure that grunt boots. Change-Id: I045a941ed42fcc4f2dbdd65b5cbb42d84813f50c Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28244 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12libpayload/x86/apic: Add an apic_delay method and calibrate the timerRaul E Rangel
The apic_delay method will halt the CPU and wait for a timer interrupt to fire. I went with usec because nsec is too granular to guarantee. This method will be called from an arch_ndelay() method when the delay is large enough to justify a sleep. BUG=b:109749762 TEST=Tested it on grunt by changing the _delay method to call apic_delay(). Change-Id: I80363f06bdb22d0907f895885e607fde1c4c468d Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-12libpayload/arch/x86: Add support for initializing the APICRaul E Rangel
This is just the bare minimum required to initialize the APIC. I only support xAPIC and chose not to support x2APIC. We can add that functionality later when it's required. I also made the exception dispatcher call apic_eoi so that the callbacks won't forget to call it. BUG=b:109749762 TEST=Booted grunt and verified that depthcharge continued to function and that linux booted correctly. Also verified GDB still works. Change-Id: I420a4eadae84df088525e727b481089ef615183f Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-10libpayload/x86/gdb: Migrate to use set_interrupt_handlerRaul E Rangel
BUG=b:109749762 TEST=Verified GDB still functions by hitting Ctrl+G on the developer screen and stepping through some code. Change-Id: I723a8a95f681c500d9d8e35e49fd1d893cb1f133 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-10libpayload/x86/exception: Add ability to handle user defined interruptsRaul E Rangel
I need to setup the APIC timer to fire interrupts. I would like to reuse the existing interrupt table. So I extended it to support user defined interrupts. I just added all 255 vectors so there wouldn't need to be any additional build time configuration. I'm going to deprecate exception_install_hook and remove it in a follow up. It will be replaced with set_interrupt_handler. This way the exception lookup does not have to manage a list of callbacks, or have to worry about the order they are processed. BUG=b:109749762 TEST=Wrote an interrupt handler and fired an APIC timer interrupt and verified that vector 32 was returned. Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-23libpayload/x86/exception: Add methods to enable/disable interruptsRaul E Rangel
Will be used by the APIC. BUG=b:109749762 TEST=Verified by the other cls in the stack. Change-Id: Id86f2719d98a90318ac625e09601e5dbb06e3765 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06exception: Fix segment error code maskRaul E Rangel
The segment error descriptor is actually 13 bits long. BUG=b:109749762 TEST=Verified by causing a segment error Change-Id: I3439f9ce1e8cf0c472c4eb82d74a787718c9609f Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-08libpayload-x86: Enable SSE and FPU when presentPatrick Rudolph
Allows to use SSE and floating point in payloads without digging to much into x86 assembly code. Tested on Lenovo T500 (Intel Core2Duo). Both floating point operation and SSE is properly working. Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18345 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-17libpayload: multiboot - support meminfo flagMathias Krause
Some simple implementation of the MultiBoot protocol may not pass a memory map (MULTIBOOT_FLAGS_MMAP missing in the flags) but just the two values for low and high memory, indicated by the MULTIBOOT_FLAGS_MEMINFO flag. Support those kind of boot loaders too, instead of falling back to the hard-coded values in lib_get_sysinfo(). Tested with a multiboot enhanced version of FILO. Change-Id: I22cf9e3ec0075aff040390bd177c5cd22d439b81 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: https://review.coreboot.org/18350 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-17libpayload: x86/head - implement argc/argv handlingMathias Krause
Implement the argc/argv passing as described in coreboot’s payload API: http://www.coreboot.org/Payload_API While at it, give the code some love by not needlessly trashing register values. Change-Id: Ib830f2c67b631b7216843203cefd55d9bb780d83 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: https://review.coreboot.org/18336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-17libpayload: x86/exec - simplify and robustify the codeMathias Krause
Simplify the code by directly using the arguments on the stack as base pointer relative memory references, instead of loading them into intermediate registers first. Make it more robust by preserving all callee saved registers mandated by the C calling convention (and only those), namely EBP, EBX, ESI and EDI. Don't assume anything about the register state when the called function returns -- beside the segment registers and the stack pointer to be still the same as before the call. Change-Id: I383d6ccefc5b3d5cca37a1c9b638c231bbc48aa8 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: https://review.coreboot.org/18335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-17libpayload: x86/main - propagate return value of main()Mathias Krause
According to coreboot’s payload API [1], the called payload should be able to return a value via %eax. Support this by changing the prototype of start_main() and pass on the return value of main() to the caller instead of discarding it. [1] https://www.coreboot.org/Payload_API Change-Id: I8442faea19cc8e04487092f8e61aa4e5cba3ba76 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: https://review.coreboot.org/18334 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-17libpayload: x86/exec - fix argc/argv value passingMathias Krause
According to coreboot’s payload API [1] the argc value should be passed at stack offset 0x10, so we need to push a dummy value to comply to the API. [1] https://www.coreboot.org/Payload_API Change-Id: Id20424185a5bf7e4d94de1886a2cece3f3968371 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: https://review.coreboot.org/18333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-15libpayload: x86/exec - fix return value passingMathias Krause
The pointer to write the return value to is in %ecx, not %eax. Writing to (%eax) leads to memory corruptions as %eax holds the return value, e.g. would write zero to address zero for a "successful" returning payload. Change-Id: I82df27ae89a9e3d25f479ebdda2b50ea57565459 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: https://review.coreboot.org/18332 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-15libpayload: x86/exec - fix libpayload API magic valueMathias Krause
According to coreboot’s payload API [1] the magic value passed to the payload should be 0x12345678, not 12345678. Fix that. [1] https://www.coreboot.org/Payload_API Change-Id: I10a7f7b1a4aec100416c5e7e4ba7f8add10ef5c5 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: https://review.coreboot.org/18331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-13libpayload: head.S: Avoid clearing BSS (and heap) againJulius Werner
3 out of 4 architectures currently zero out the payload BSS in early assembly code, which is pointless since the code loading the payload has already done that (with a more efficient memset). ARM64 has never had any code like this and can run just fine without it. This also defeats the new optimization of moving the heap out of the BSS, since all three implementations assume that everything between _edata and _end is BSS. We should just take this out. Change-Id: I45cd2dabd94da43ff0f77e990f11c877cee6cda1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16091 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-15libpayload: Move base address, stack and heap size to KconfigStefan Reinauer
This will allow more payloads to use the standard linker script instead of implementing their own. Change-Id: Ie60120769829f427ceb722109d85859b61dbde31 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19libpayload: honor TSC information under CONFIG_LP_TIMER_RDTSCAaron Durbin
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information exported in the coreboot tables as the cpu_khz frequency. That allows get_cpu_speed() not to be called which currently relies on the 8254 PIT. As certain x86 platforms allow that device to be optional or turned off for power saving reasons, allow a path where get_cpu_speed() is no longer called. Additionally, this approach also allows the libpayload to not duplicate logic that already exists in coreboot. BUG=chrome-os-partner:50214 BRANCH=glados TEST=Confirmed in payload TSC frequency is honored instead of using get_cpu_speed(). Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13671 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-07Drop "See file CREDITS..." commentStefan Reinauer
coreboot has no CREDITS file. Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11514 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01libpayload: Keep stack boundary small on x86Stefan Reinauer
There is no measurable performance impact, but this positively impacts the memory used by payloads. Change-Id: Ib2bdba4a7bf2a4c2391a20b3225bbb44422d3194 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10751 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-30libpayload: Make Kconfig bools use IS_ENABLED()Stefan Reinauer
This will make the code work with the different styles of Kconfig (emit unset bools vs don't emit unset bools) Roughly, the patch does this, and a little bit of fixing up: perl -pi -e 's,ifdef (CONFIG_LP_.+?)\b,if IS_ENABLED\($1\),g' `find . -name *.[ch]` perl -pi -e 's,ifndef (CONFIG_LP_.+?)\b,if !IS_ENABLED\($1\),g' `find . -name *.[ch]` Change-Id: Ib8a839b056a1f806a8597052e1b571ea3d18a79f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10711 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-12libpayload: Rename Config.in -> KconfigStefan Reinauer
libpayload is the only Kconfig based project under the coreboot umbrella that is using Config.in as its name for Kconfig config files. Rename that to Kconfig as on the other projects for consistency. Change-Id: I1c69ec13582d88409384b492484535dcc5e1ad20 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10520 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-08Remove empty lines at end of fileElyes HAOUAS
Used command line to remove empty lines at end of file: find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \; Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/10446 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-03-20libpayload: move MRC processing to x86 path and remove ACPI_GNVS duplicationVadim Bendebury
It turns out that CB_TAG_ACPI_GNVS is handled in both x86 specific and common coreboot table parsing code. The MRC cache case used only by x86 is handled in the common code. This patch restores sanity and moves processing to where it belongs. BRANCH=none BUG=none TEST=verified that arm and x86 targets build. Change-Id: Iaddaa3380725be6d08a51a96c68b70522531bafe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0afae893d5027026cb666cd46e054aeae4e71f83 Original-Change-Id: I2c114a8469455002c51593cb8be80585925969a7 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225457 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20libpayload: Consolidate coreboot table parsingVadim Bendebury
There are three instances of coreboot.c in libpayload. for x86, arm and arm64 architectures. The arm and arm64 instances are exactly the same. The differences with the x86 instance are as follows: - a very slightly different set of coreboot table tags is parsed (one tag added and two removed) - instead of checking a fixed address if it contains the coreboot table, the x86 version iterates over two address ranges. This patch refactors the module, leaving architecture specific processing in arch subdirectories and moving the common code into libc. BUG=none TEST=none yet Change-Id: I1c7ad6f74e3498e93df78086ba0ff708c08e0a5c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3df209d58ebd5c5b1cf0168f6466e065d1ef3598 Original-Change-Id: I6dfed73f6ba5939f692d0f98d2774c0e0312a25f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210770 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8750 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-20libpayload: Add board id parsingVadim Bendebury
Make board ID value supplied in the coreboot table available to the bootloader on all three architectures. BUG=chrome-os-partner:30489 TEST=none yet Change-Id: I6c2d39e94212b55650929d7d99896581d23f789d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 723e4a600a5d3a03e960169b04f8322f6dd2486b Original-Change-Id: I7847bd9fe2d000a29c7ae95144f4868d926fb198 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210430 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8730 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-01-09libpayload: Add remote GDB supportJulius Werner
This patch adds the ability to attach a GDB host through the UART to a running payload. Libpayload implements a small stub that can parse and respond to the GDB remote protocol and provide the required primitives (reading/writing registers/memory, etc.) to allow GDB to control execution. The goal of this implementation is to be as small and uninvasive as possible. It implements only the minimum amount of primitives required, and relies on GDB's impressive workaround capabilities (such as emulating breakpoints by temporarily replacing instructions) for the more complicated features. This way, a relatively tiny amount of code on the firmware side opens a vast range of capabilities to the user, not just in debugging but also in remote-controlling the firmware to change its behavior (e.g. through GDBs ability to modify variables and call functions). By default, a system with the REMOTEGDB Kconfig will only trap into GDB when executing halt() (including the calls from die_if(), assert(), and exception handlers). In addition, payloads can manually call gdb_enter() if desired. It will print a final "Ready for GDB connection." on the serial, detach the normal serial output driver and wait for the commands that GDB starts sending on attach. Based on original implementation by Gabe Black <gabeblack@chromium.org>. BUG=chrome-os-partner:18390 TEST=Boot a GDB enabled image in recovery mode (or get it to hit a halt()), close your terminal, execute '<toolchain>-gdb --symbols /build/<board>/firmware/depthcharge_gdb/depthcharge.elf --directory ~/trunk/src/third_party/coreboot/payloads/libpayload --directory ~/trunk/src/platform/depthcharge --directory ~/trunk/src/platform/vboot_reference --ex "target remote <cpu_uart_pty>"' and behold the magic. (You can also SIGSTOP your terminal's parent shell and the terminal itself, and SIGCONT them in reverse order after GDB exits. More convenient wrapper tools to do all this automatically coming soon.) Original-Change-Id: Ib440d1804126cdfdac4a8801f5015b4487e25269 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202563 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 9c4a642c7be2faf122fef39bdfaddd64aec68b77) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9238b4eb19d3ab2c98e4e1c5946cd7d252ca3c3b Reviewed-on: http://review.coreboot.org/8119 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09libpayload: Introduce new Kconfig to explicitly allow GPL codeJulius Werner
There have been leaks of GPL code into libpayload for a while now, for new features or improvements that require third party code with no adequate alternative among BSD-licensed software. It seems silly and counter-productive to keep holding back features and performance improvements from libpayload for a use-case (proprietary payloads) that doesn't even seem to be implemented anywhere to date. Open-source payloads should not need to suffer to appease commercial ones. Instead, this patch introduces a new Kconfig option to explicitly allow inclusion of GPL code. It will use Kconfig dependencies and/or Makefile rules to ensure that no GPL code can end up in the final payload if that option is unset, allowing proprietary payloads to keep working with the existing BSD-licensed feature set. New features and patches (that are sufficiently separate and self-contained to allow guarding through this config option) can choose whether to import GPL code, and need to depend on this option if they do. Also clean up all (known) existing uses of GPL code to depend on the new option, add some recent third-party imports to the LICENSES file, and relicense the selfboot.c files to BSD with permission of the author. BUG=chrome-os-partner:24957 TEST=Compiled Falco and Nyan_Big both with and without the new option, disassembled output binaries to ensure that memcpy() looks as expected. Original-Change-Id: I6e3a75b1a8e46291c75a876844c7a01f7d3f2a0e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203513 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit d8e5a9fdf583b5ac861f34baea6a16c4d8536512) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I446fef028264c793b946dd9f765e446bf708b4db Reviewed-on: http://review.coreboot.org/8118 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09libpayload: Rework exception hook interfaceJulius Werner
This patch makes some slight changes to the exception hook interface. The old code provides a different handler hook for every exception type... however, in practice all those hook functions often need to look very similar, so this creates more boilerplate than it removes. The new interface just allows for a single hook with the exception type passed as an argument, and the consumer can signal whether the exception was handled through the return value. (Right now this still only supports one consumer, but it could easily be extended to walk through a list of hooks if the need arises.) Also move the excepton state from an argument to a global. This avoids a lot of boilerplate since some consumers need to change the state from many places, so they would have to pass the same pointer around many times. It also removes the false suggestion that the exception state was not global and you could have multiple copies of it (which the exception core doesn't support for any architecture). On the ARM side, the exception state is separated from the exception stack for easier access. (This requires some assembly changes, and I threw in a few comments and corrected the immediate sigils from '$' to the official '#' while I'm there.) Since the exception state is now both stored and loaded through an indirection pointer, this allows for some very limited reentrance (you could point it to a different struct while handling an exception, and while you still won't be able to return to the outer-level exception from there, you could at least swap out the pointer and return back to System Mode in one go). BUG=chrome-os-partner:18390 TEST=Made sure normal exceptions still get dumped correctly on both archs. Original-Change-Id: I5d9a934fab7c14ccb2c9d7ee4b3465c825521fa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202562 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 97542110f0b385b9b8d89675866e65db8ca32aeb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> *** Squashed to prevent build failures. *** libpayload: align arm64 with new exception handling model The exception handling was previously updated, however the arm64 changes raced with hat one. Make the arm64 align with the new model. Without these changes compilation will fail. BUG=None BRANCH=None TEST=Can build libpayload for rush. Original-Change-Id: I320b39a57b985d1f87446ea7757955664f8dba8f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204402 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0080df41b311ef20f9214b386fa4e38ee54aa1a1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9a0bb3848cf5286f9f4bb08172a9f4a15278348e Reviewed-on: http://review.coreboot.org/8117 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-30libpayload: don't dereference null pointer in exception handlerPatrick Georgi
Change-Id: I93e5e2488ddd616c91769beb1acd96f8ebd7d505 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/7971 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-30libpayload: Add missing break statementPatrick Georgi
Change-Id: I073b9bd30f4f9b0cdf6c45c10e4549889342d5f3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/7970 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-30libpayload: Remove useless continue after returnPatrick Georgi
Change-Id: I7209ceaf4ad686bbb07eb0c6105f77834d5511fd Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/7969 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-30libpayload: Provide selfboot function.Hung-Te Lin
The calling convention of payload entry function is different by architecture. For example, X86 takes no arguments and ARM needs first param to be a cb_header_ptr*. To help payloads load and execute other payloads easily and correctly, we should provide the selfboot() function in libpayload, using same prototype as defined in coreboot environment. BUG=none TEST=emerge-nyan libpayload # pass BRANCH=none Original-Change-Id: I8f1cb2c0df788794b2f6f7f5500a3910328a4f84 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199503 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 1e916cf021ce68886eb9668982c392eadedc7b7e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7279ef27f49ef581d25a455dd8f1f2f7f1ba58cb Reviewed-on: http://review.coreboot.org/7907 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-09libpayload: Make it possible to install callbacks for particular exceptions.Gabe Black
To support a GDB stub, it will be necessary to trap various exceptions which will be used to implement breakpoints, single stepping, etc. BUG=None TEST=Built and booted on Link with hooks installed and saw that they triggered when exceptions occurred. Built and booted on nyan. BRANCH=None Original-Change-Id: Iab659365864a3055159a50b8f6e5c44290d3ba2b Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/179602 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8db0897b1ddad600e247cb4df147c757a8187626) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5e7f724b99988cd259909dd3bd01166fa52317ec Reviewed-on: http://review.coreboot.org/7656 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-11-13libpayload: timer: Move the timer drivers from depthcharge to libpayload.Gabe Black
These drivers are needed right away and never really fit into depthcharge's driver model anyway. CQ-DEPEND=CL:194064 BUG=None TEST=Built and booted nyan, link, and peach_pit and verified that timer values in cbmem were reasonable. Built for nyan_big, nyan_blaze and daisy. BRANCH=None Original-Change-Id: Ia7953cfece57524262a6c7d6537082af7a00f4d6 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194058 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit f30a410f0a248c93bc34f5868af1596bf8ce3cdd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I782d20f3cd63210a87c712643c7a53753f5ef301 Reviewed-on: http://review.coreboot.org/7225 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-09-15libpayload: x86: Add support for catching processor exceptions.Gabe Black
This functionality is already available for ARM, so lets add it to x86 as well. We'll want to be able to hook exceptions when running as a remote GDB target. Change-Id: I42f640b08eb9eb86a1bcab3c327f7780191a2eb5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/179601 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5b8cf0c9f70a7e14766a2b095e6739a8d6321a34) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6898 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-10coreboot_tables: reduce redundant data structuresJulius Werner
There are three coreboot table tags that all define some kind of memory region, and each has their own homologous struct. I'm about to add a fourth so I'll just clean this up and turn it into a generic struct lb_range instead. Change-Id: Id148b2737d442e0636d2c05e74efa1fdf844a0d3 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167154 (cherry picked from commit 22d82ffa3f5500fbc1b785e343add25e61f4f194) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6456 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-05libpayload: Change CONFIG_* to CONFIG_LP_* in the kconfig.Gabe Black
When libpayload header files are included in the payload itself, it's possible that the payloads config settings will conflict with the ones in libpayload. It's also possible for the libpayload config settings to conflict with the payloads. To avoid that, the libpayload config settings have _LP_ (for libpayload) added to them. The symbols themselves as defined in the Config.in files are still the same, but the prefix added to them is now CONFIG_LP_ instead of just CONFIG_. Change-Id: Ib8a46d202e7880afdeac7924d69a949bfbcc5f97 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65303 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 23e866da20862cace0ed2a67d6fb74056bc9ea9a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6427 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-01-30libpayload: Parse CBMEM ACPI GNVS pointerDuncan Laurie
Pull the ACPI GNVS pointer from CBMEM and expose it in the sysinfo structure for use by payloads. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi with emmc in ACPI mode Change-Id: I47c358f33c464a4a01080268fb553705218c940c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179900 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5016 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-12libpayload: Get rid of a compiler warningGabe Black
Change-Id: I7252925ef5c4efb69cad6b6fa179031162cf8e74 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61058 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4346 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29libpayload: add x86 ROM variable MTRR supportAaron Durbin
On x86, coreboot may allocate a variable range MTRR for enabling caching of the system ROM. Add the ability to parse this structure and add the result to the sysinfo structure. An example usage implementation would be to obtain the variable MTRR index that covers the ROM from the sysinfo structure. Then one would disable caching and change the MTRR type from uncacheable to write-protect and enable caching. The opposite sequence is required to tearn down the caching. Change-Id: I3bfe2028d8574d3adb1d85292abf8f1372cf97fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22libpayload: Add comments on virtual pointers in lib_sysinfoNico Huber
After another incident related to virtual pointers in lib_sysinfo (and resulting confusion), I decided to put some comments on the matter into the code. Remember, we decided to always use virtual pointers in lib_sysinfo, but it's not always obvious from the code, that they are. See also: 425973c libpayload: Always use virtual pointers in struct sysinfo_t 593f577 libpayload: Fix use of virtual pointers in sysinfo Change-Id: I886c3b1d182cba07f1aab1667e702e2868ad4b68 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/2878 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-14libpayload: add support for vboot_handoffAaron Durbin
The vboot_handoff structure needs to be parsed from the coreboot tables. Add a placeholder in sysinfo as well as the ability to parse the coreboot table entry concering the vboot_handoff structure. Built with unified boot loader and ebuild changes. Can find and use the VbInitParams for doing kernel selection. Change-Id: If40a863b4a445fa5f7814325add03355fd0ac647 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2720 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14libpayload: Generalize and redistribute timekeeping codeGabe Black
The timekeeping code in libpayload was dependent on rdtsc, and when it was split up by arch, that code was duplicated even though it was mostly the same. This change factors out actually reading the count from the timer and the speed of the timer and puts the definitions of ndelay, udelay, mdelay and delay into generic code. Then, in x86, the timer_hz and timer_get_raw_value functions which used to be in depthcharge were moved over to libpayload's arch/x86/timer.c. In ARM where there isn't a single, canonical timer, those functions are omitted with the intention that they'll be implemented by a specific timer driver chosen elsewhere. Change-Id: I9c919bed712ace941f417c1d58679d667b2d8269 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2717 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13libpayload: Make whether or not there's an IO address space configurableGabe Black
Default it to no to be consistent with the other architecture wide options (endianness), and turn it on explicitly for x86 and PowerPC. Change-Id: Idda26d580156bbbf08ea11b28abe75cfa6b594b2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2658 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-26libpayload: Change the measurement interval for get_cpu_speed to 2 ms.Gabe Black
The interval used to be about 55 ms which is excessively long. Coreboot only waits for 2 ms and gets a reasonable answer. That should be good enough for us as well. Change-Id: I4d4e8b25b6ba540c9e9839ed0bbaa1f04f67cce1 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2520 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-20libpayload: Fix license headersStefan Reinauer
Not only were these files checked in with the Chromium OS Authors copyright, but in addition they were wrongly licensed as GPL. Switch to 3-clause BSD (and, since we're changing it, fix copyright, too) Change-Id: I3656c1f4304d53e343d89bb7c909fd4b929249f4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2456 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14libpayload; put the ldscript into an arch-dependent directory pathRonald G. Minnich
Since it's utterly architecture-dependent, put it in arch/x86. Avoid the temptation to make yet another directory with just one file in it. Fix the makefile to pick up the proper arch-dependent script. Change-Id: I21ea02551a97bdcbc38419714f3b38cf8335c178 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2389 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-12libpayload: New CBFS to support multiple firmware media sources.Hung-Te Lin
Upgrade CBFS in libpayload to use new media-based implementation from coreboot ( http://review.coreboot.org/#/c/2182/ ). Old CBFS functions (cbfs_find, cbfs_find_file, get_cbfs_header) are still supported, although the recommended way is to use new CBFS API. To migrate your existing x86 payload source: - Change cbfs_find to cbfs_get_file - Change cbfs_find_file to cbfs_get_file_content - Prefix every CBFS call with a CBFS_DEFAULT_MEDIA argument. Ex, char *jpeg_data = cbfs_find_file("splash.jpg", CBFS_TYPE_BOOTSPLASH); => char *jpeg_data = cbfs_get_file_content( CBFS_DEFAULT_MEDIA, "splash.jpg", CBFS_TYPE_BOOTSPLASH); The legacy setup_cbfs_from_{ram,flash} is also supported, although the better equivalent is to make a new media instance: struct cbfs_media ram_media; init_cbfs_ram_media(&ram_media, start, size); char *data = cbfs_get_file_content(&ram_media, "myfile", my_type); Verified by being successfully linked with filo. Change-Id: If797bc7e3ba975d7e3be905c59424f7a93b8ce11 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2191 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-12-14libpayload: rename i386 to x86Stefan Reinauer
Change-Id: Ia9170bd3d04e76dbf9321ca7ea4be23b5e468d21 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2033 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 18:00:55 +0000