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2018-06-14src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
pci_bus_default_ops() is the default anyway. Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-17Documentation/Intel: Adjust heading levelsJonathan Neuschäfer
Adjust the headings so that there is only one h1 tag per file. Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-12Documentation: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Unfortunately, some external websites and projects are spelling coreboot with an uppercase C, so references to those pages can't be changed without breaking the link. Change-Id: I79824da8a9ed36a1e4fe23a1711a89535267bf5f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-30Documentation/Intel/Soc: Update Quark FSP build instructionsLee Leahy
Update the FSP build instructions for Quark: * Discuss multiple types BRANCH=none BUG=None TEST=Build Quark FSP using new instructions Change-Id: Ibc4bfe32d0eb3877d3b988bc185c73be58d44878 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18Documentation/Intel: Update the documentationLee Leahy
index.html: * Separate the sections on the main page * Move the documentation links to the main page * Add links for FSP 1.0 and 2.0 specifications * Add link for UEFI specifications * Add link to MinnowBoard MAX coreboot fsp1_1.html: * Use Integration instead of Documentation SoC/quark.html: * Move documentation to main page * Update build instructions for CorebootPayloadPkg * Remove FatPkg since it is now part of edk2 tree * Add source location for QuarkFspPkg * Add build instructions for QuarkFspPkg TEST=None Change-Id: I48bd1bf98a6d8bc43bdd3b4c51dfd119a1e0f61b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14882 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21Documentation: x86 shadow ROM disableLee Leahy
Add documentation on disabling the SPI flash which is mapped (shadowed) into the x86 address space at 0x000e0000 - 0x000fffff. TEST=None Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/14112 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-07Documentation/Intel: Add EDK-II linksLee Leahy
Add a link to the "Driver Writer's Guide" and a link to the "EDK II firmware for Intel Quark SoC X1000" document. TEST=None Change-Id: I8d629d06accfe24a0b8971b5b5868849587c3db7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13893 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-02-29Documentation/Intel: More CorebootPayloadPkg documentationLee Leahy
Add more documentation on the features that the EDK-II CorebootPayloadPkg is using. Add 8254 and 8259 documentation links. Add EDK-II documentation links. TEST=Boot CorebootPayloadPkg to shell prompt Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-29Documentation/Intel: Add ACPI link and more FADT documentationLee Leahy
Add a link to the ACPI specification. Update the FADT table to better describe the use and ACPI specification reference for the various fields. TEST=None Change-Id: I77cd925800d71398be6d677de48874099ea26479 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13765 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-24Documentation/Intel: Add minimal APCI and TempRamExit documentationLee Leahy
Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-22Documentation/Intel: Update EDK2 CorebootPayloadPkg build instructionsLee Leahy
Update the build instructions for CorebootPayloadPkg to target the Galileo Gen2 platform. TEST=Build and run on the Galileo Gen2 platform. Change-Id: I9ca8a67811eff988f81f04d4c01c77115356c050 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13756 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-19Documentation: x86 device tree processing and memory mapLee Leahy
Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19Documentation: x86 add EDK2 CorebootPayloadPkg and documentation linksLee Leahy
Add EDK2 CorebootPayloadPkg build instructions, EDK2 documentation links and EDK2 BIOS build instructions. TEST=None Change-Id: I236405914c5fa8e33a7826cc4fa60f6dbf0e7724 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13717 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09Documentation: Add Quark EDK2 build instructions for LinuxLee Leahy
Document the Linux build instructions for EDK2. TEST=Build EDK2 for Quark on Ubuntu 14.04 Change-Id: I5f87eb2c5879f2fd4dd18880908756089a0c7a51 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13644 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05Documentation: x86 add sleep state and minimal memory setupLee Leahy
Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05Documentation: x86 Enable Serial OutputLee Leahy
Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13444 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05Documentation: Add the x86 FSP BinaryLee Leahy
Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13442 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05Documentation: Fix links to Intel/documentation.htmlLee Leahy
Fix links to the documenation.html page which was renamed from x86Documenation.html. TEST=Verified documentation links and searched for x86Documenation.html Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13592 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04Documentation: Add x86 bootblock supportLee Leahy
Document what is involved with adding the bootblock support. TEST=None Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13441 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02Documenation: x86 Quark/Galileo remove i586 warningLee Leahy
Leverage patch 13552 by adding USE_MARCH_586 to soc/intel/quark/Kconfig. TEST=None Change-Id: Ifac947db53e967b98b9494db3f6c3f8ee039ac73 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13561 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-02Documentation: Add x86 documentation for required filesLee Leahy
Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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