diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-01-07 11:24:24 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-02-02 15:54:43 +0100 |
| commit | c1e4f8995362c6eb7d09dfc0618edcc636d30acc (patch) | |
| tree | f5639a152232579412a3a9da0e4cd224f30505e8 /Documentation/Intel/SoC | |
| parent | 2f91403303a66c5e724761a74863e3452291b154 (diff) | |
Documentation: Add x86 documentation for required files
Document the required files to perform a minimal coreboot/FSP build for
x86.
TEST=None
Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'Documentation/Intel/SoC')
| -rw-r--r-- | Documentation/Intel/SoC/quark.html | 98 | ||||
| -rw-r--r-- | Documentation/Intel/SoC/soc.html | 105 |
2 files changed, 203 insertions, 0 deletions
diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html new file mode 100644 index 0000000000..14dd5076b3 --- /dev/null +++ b/Documentation/Intel/SoC/quark.html @@ -0,0 +1,98 @@ +<!DOCTYPE html> +<html> + <head> + <title>Quark™ SoC</title> + </head> + <body> + +<h1>Intel® Quark™ SoC</h1> +<table> + <tr> + <td><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png"><img alt="Quark Block Diagram" src="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png" width=500></a></td> + <td> +<table> + <tr bgcolor="#ffc0c0"> + <td> +Warning: Use of the Intel® Quark™ SoC code requires modification of the util/xcompile/xcompile file to change the machine +architecture from i686 to i586 because the Quark™ processor does not support the instructions +introduced with the Pentium™ 6 architecture. +<ol> + <li>Edit the file util/xcompile/xcompile</li> + <li>Search for +<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=util/xcompile/xcompile;hb=HEAD#l185">-march</a></li> + <li>Replace i686 with i586</li> + <li>Save the result</li> +</ol> +Without this change the Quark™ processor will halt when it executes one of the +instructions introduced with the Pentium™ 6 architecture. + </td> + </tr> +</table> +<p> + The Quark™ SoC code was developed using the + <a target="_blank" href="../Board/galileo.html">Galileo Gen 2</a> + board: +</p> +<ul> + <li><a target="_blank" href="../x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="soc.html">SoC</a> support</li> + <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="../Board/board.html">Board</a> support</li> +</ul> + </td> + </tr> +</table> + + + +<hr> +<h1>Quark™ Documentation</h1> +<ul> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png">Block Diagram</a></li> + <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf">Software Developer Manual</a></li> + <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/quark/specifications.html">Specifications</a>: + <ul> + <li><a target="_blank" href="http://ark.intel.com/products/79084/Intel-Quark-SoC-X1000-16K-Cache-400-MHz">X1000</a> + - <a target="_blank" href="http://www.intel.com/content/www/us/en/search.html?keyword=X1000">Documentation</a>: + <ul> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quark-x1000-datasheet.pdf">Datasheet</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/support/us/en/documents/processors/quark/sb/intelquarkcore_devman_001.pdf">Developer's Manual</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/intel-quark-product-brief-v3.pdf">Product Brief</a></li> + </ul> + </li> + </ul> + </li> +</ul> + + + +<hr> +<h1>Quark™ FSP</h1> +<ul> + <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li> + <li>Intel® Quark™ SoC X1000 <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x1000-uefi-firmware-writers-guide.pdf">UEFI Firmware Writer's Guide</a></li> + <li>EDK2 Sources: + <ul> + <li>EDK2: git clone <a target="_blank" href="https://github.com/tianocore/edk2.git">https://github.com/tianocore/edk2.git</a></li> + <li>EDK2-FatPkg: git clone <a target="_blank" href="https://github.com/tianocore/edk2-FatPkg.git">https://github.com/tianocore/edk2-FatPkg.git</a> FatPkg</li> + <li>EDK2-non-osi: git clone <a target="_blank" href="https://github.com/tianocore/edk2-non-osi.git">https://github.com/tianocore/edk2-non-osi.git</a></li> + <li>Win32 BaseTools: git clone <a target="_blank" href="https://github.com/tianocore/edk2-BaseTools-win32.git">https://github.com/tianocore/edk2-BaseTools-win32.git</a></li> + </ul> + </li> + <li>Win32 Build Instructions: +<pre><code>set WORKSPACE=%CD% +set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\FatPkg;%WORKSPACE%\edk2-non-osi +set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32 +cd edk2 +edksetup.bat +build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 +</code></pre> + </li> +</ul> + + + +<hr> +<p>Modified: 30 January 2016</p> + </body> +</html>
\ No newline at end of file diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html new file mode 100644 index 0000000000..30821dcd9c --- /dev/null +++ b/Documentation/Intel/SoC/soc.html @@ -0,0 +1,105 @@ +<!DOCTYPE html> +<html> + <head> + <title>SoC</title> + </head> + <body> + +<h1>x86 System on a Chip (SoC) Development</h1> +<p> + SoC development is best done in parallel with development for a specific + board. The combined steps are listed + <a target="_blank" href="../x86Development.html">here</a>. + The development steps for the SoC are listed below: +</p> +<ol> + <li><a target="_blank" href="../fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> + <li>SoC <a href="#RequiredFiles">Required Files</a></li> + <li><a href="#Descriptor">Start Booting</a></li> + <li><a href="#EarlyDebug">Early Debug</a></li> +</ol> + + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<p> + Create the directory as src/soc/<Vendor>/<Chip Family>. +</p> + +<p> + The following files are required to build a new SoC: +</p> +<ul> + <li>Include files + <ul> + <li>include/soc/pei_data.h</li> + <li>include/soc/pm.h</li> + </ul> + </li> + <li>Kconfig - Defines the Kconfig value for the SoC and selects the tool + chains for the various stages: + <ul> + <li>select ARCH_BOOTBLOCK_<Tool Chain></li> + <li>select ARCH_RAMSTAGE_<Tool Chain></li> + <li>select ARCH_ROMSTAGE_<Tool Chain></li> + <li>select ARCH_VERSTAGE_<Tool Chain></li> + </ul> + </li> + <li>Makefile.inc - Specify the include paths</li> + <li>memmap.c - Top of usable RAM</li> +</ul> + + +<hr> +<h1><a name="Descriptor">Start Booting</a></h1> +<p> + Some SoC parts require additional firmware components in the flash. + This section describes how to add those pieces. +</p> + +<h2>Intel Firmware Descriptor</h2> +<p> + The Intel Firmware Descriptor (IFD) is located at the base of the flash part. + The following command overwrites the base of the flash image with the Intel + Firmware Descriptor: +</p> +<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre> + + +<h2><a name="MEB">Management Engine Binary</a></h2> +<p> + Some SoC parts contain and require that the Management Engine (ME) be running + before it is possible to bring the x86 processor out of reset. A binary file + containing the management engine code must be added to the firmware using the + ifdtool. The following commands add this binary blob: +</p> +<pre><code>util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom +mv build/coreboot.rom.new build/coreboot.rom +</code></pre> + + +<h2><a name="EarlyDebug">Early Debug</a></h2> +<p> + Early debugging between the reset vector and the time the serial port is enabled + is most easily done by writing values to port 0x80. +</p> + + +<h2>Success</h2> +<p> + When the reset vector is successfully invoked, port 0x80 will output the following value: +</p> +<ul> + <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a> + - Bootblock successfully executed the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a> + and entered the 16-bit code at + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a> + </li> +</ul> + + +<hr> +<p>Modified: 31 January 2016</p> + </body> +</html>
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