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2021-02-16mb/prodrive/hermes: Improve board config EEPROM handlingAngel Pons
* Check and print errors returned from reading from I2C * Rework offset calculation by using more macros * Get rid of stage-specific preprocessor code * Define the EEPROM layout as struct * Make use of the defined EEPROM layout to calculate offsets * Read the UPD to disable VT-d from EEPROM Change-Id: Iad77811318c7dfd3a3a4f8d523cfa0f457f168b6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48808 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16nb/intel/sandybridge: Fix description of auto-precharge bitAngel Pons
This bit is primarily used to issue RDA commands. There doesn't seem to be any limitation regarding the number of address bits. Change-Id: I2804f67319c9bc736f9086af408853056aabedd6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-16vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
Always allocate RAMOOPS from CBMEM and drop the related static variable CHROMEOS_RAMOOPS_RAM_START. Change-Id: Icfcf2991cb78cc6e9becba14cac77a04d8ada56a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50608 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
Change-Id: I4ec59cea256a39a94b05cdeb8f914830ac0bd3f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16nb/intel/sandybridge,haswell: Use chromeos_reserve_ram_oops()Kyösti Mälkki
Communicate the RAMOOPS section via ChromeOS GNVS. Change-Id: I75170e6e34c20db88efa268080d2c38916b31f37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16soc/intel: Switch guard to CHROMEOS_RAMOOPSKyösti Mälkki
Change-Id: I484220342b5c1055471403f562a8c9db6a403a05 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16soc/inteL/broadwell: Move select CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
With this selected, chromeos_reserve_ram_oops() is a no-op. Change-Id: I2f3b7b3c4a9549a14f2ba039c769546f9698409a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16ACPI: Add acpi_reset_gnvs_for_wake()Kyösti Mälkki
With chipset_power_state filled in romstage CBMEM hooks and GNVS allocated early in ramstage, GNVS wake source is now also filled for normal boot path. Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-16src/acpi: Add missing <types.h>Elyes HAOUAS
Change-Id: Iec78183b43ea26d9de14e0ce28eef6fc0361cc95 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16console/vtxprintf.c: Add missing <types.h>Elyes HAOUAS
Change-Id: Icc2b99f9125e9059dbf3de42a1b5ca9727888166 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16nb/i945/raminit.c: Don't hard code 'bool integrated_graphics'Elyes HAOUAS
Change-Id: I735fa6413128cb9c17d99dfe9ffc3ee93ede51ae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-16util/bincfg: Fix all issuesMartin Roth
This fixes the following issues: bincfg.l: In function ‘parsehex’: error: declaration of ‘val’ shadows a global declaration bincfg.y: In function ‘generate_binary_with_gbe_checksum’: error: comparison of integer expressions of different signedness bincfg.y: In function ‘yyerror’: bincfg.y:408:28: error: unused parameter ‘fp’ bincfg.y: In function ‘main’: bincfg.y:452:15: error: unused variable ‘pos’ bincfg.y:451:16: error: unused variable ‘c’ BUG=None TEST=Build outputs and make sure they're identical. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I60039b741c226a6b6ba53306f6fa293da89e5355 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16util/archive: Clean up MakefileMartin Roth
- Add warnings - Enable warnings as errors: - Add distclean target - Add help target BUG=None TEST=make help; make all; make all WERROR="" Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I1ae8a837003491f3ab123b3761e220556258e0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-16util/archive: fix warningsMartin Roth
Gets rid of these 4 warnings: archive.c: In function ‘set_file_name’: warning: comparison of integer expressions of different signedness archive.c: In function ‘add_file’: warning: comparison of integer expressions of different signedness archive.c: In function ‘archive_files’: warning: comparison of integer expressions of different signedness archive.c: In function ‘convert_endian’: warning: comparison of integer expressions of different signedness BUG=None TEST=Build and run Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I57ee8b31bbc9e97168e3b818c4d053eadf8a4f84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-16util/amdfwtool: Clean up MakefileMartin Roth
- Add method to disable warnings as errors - Add help target - Add phony targets to .PHONY BUG=None TEST=make all; make help; make all WERROR="" Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Icd0cfd3e2579c9016ebb616e371d1076a5a171b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16util/amdfwtool: Enable warnings as errorsMartin Roth
BUG=None TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7746430c24dd052c435561236454b456bc597517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16util/amdfwtool: Fix all warningsMartin Roth
Fixes these warnings: warning: alignment 1 of 'struct _psp_directory_table' is less than 16 [-Wpacked-not-aligned] warning: alignment 1 of 'struct _psp_combo_directory' is less than 16 [-Wpacked-not-aligned] In function 'find_register_fw_filename_bios_dir': warning: implicit conversion from 'enum _amd_fw_type' to 'amd_bios_type' {aka 'enum _amd_bios_type'} [-Wenum-conversion] BUG=None TEST=Build and verify binaries are identical. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I761d9893ac6737b42af96c4b2a57c5a4fc61ab05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16soc/intel/baytrail,braswell: Drop aliases on MMCONF_BASE_ADDRESSKyösti Mälkki
Add MMCONF_BUS_NUMBER=256 to match previous allocation. Change-Id: I01a86481e392a9347afdc2860b58617b20c4f05a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16soc/intel: Drop aliases on MMCONF_BASE_ADDRESSKyösti Mälkki
Change-Id: I5ba60c1d8c314d37b4ef71c4613e6e0629da8149 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-16soc/amd/cezanne/data_fabric: add ACPI names and SSDT entriesFelix Held
Additionally to the PCI IDs of Cezanne it also handles the Renoir ones. The main difference between those two is that Renoir has two core complexes while Cezanne only has one core complex. I haven't seen incompatible changes between those two though, so for example the fabric IDs are the same and the one that's only present in Renoir is just not used in Cezanne. Also adding the ACPI parts for those don't have anything to do with those differences. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b2517bc15d872f41183a33857333f1972ff2cb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-15Documentation: util/board_status/README formattingAlexey Vazhnov
Improve markdown formatting. Split paragraphs to avoid too long text. Change-Id: Ia3a74460a49f28301c5e2e3b061aeb1e0eeb6c16 Signed-off-by: Alexey Vazhnov <vazhnov@boot-keys.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-15device: Add unit to Kconfig option name: `PRE_GRAPHICS_DELAY_MS`Paul Menzel
It’s good practice to put the unit into the name. Change-Id: I1493f61d4e495c22f09abf1829bb2eab9b1fd2b6 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-15src: use ARRAY_SIZE where possiblePatrick Georgi
Generated with a variant of https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/qualcomm/sc7180: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: Ie71cc6f79db9f2d722f9931e887f309e0bc9ce0b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50533 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15commonlib/cbfs.c: Remove unuse <console/console.h>Elyes HAOUAS
Change-Id: I263db3c3d26a8690b3fa493cb2e317000c4dc89d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50532 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15sb/amd: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I8c0a40a14d0a9050b83fe5e9988db70b7f94b81c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50531 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/qualcomm: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: Idd93ed91e854c8775cbcf721e4e332aef7b36e42 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50530 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/mediatek: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: If025d4c0b2ba9868d8df699fcddfcec349cdc0ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50529 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/intel: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I630b7b0b1d564bcd99358caaaef4afd78c22866c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50528 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15src/security: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I2b81a57ded80ef9c5cbdff06d8ca9d6b4f599777 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50526 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15src/nb: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I55aa05f72e06b509c85f0754320c389de7e75f8d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50525 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15src/mb: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I6e0f33172fbcecebddfccdf64c22685636a23936 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50524 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15src/drivers: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I38d565f82d078cb75f74f8502fcafdedd907b97d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50523 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15src/device: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I30ed9661d8e84be49d362baafbb2bc624952c287 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50522 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15src/arch: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: Idb80b21bb5dc4b461f89a3414d51b7d98a8328d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50521 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/lippert/frontrunner-af: Drop OSFL method in ASLKyösti Mälkki
Method only set variable OSRV, which nobody evaluates. Change-Id: I76d86af8ef6b75531f11612935dd097ee1e1a388 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-15drivers/spi: Stop using a variable-length arrayAngel Pons
Only the call in `spi_flash_cmd_write_page_program` uses non-constant values for the array length. However, the value for `data_len` has an upper bound: `flash->page_size` is set to `1U << vi->page_size_shift` which depends on the flash chip vendor info, and the largest value it can currently have is 8. Thus, the maximum page size is currently 256. Define the `MAX_FLASH_CMD_DATA_SIZE` macro to place an upper bound on the amount of data that can be written in one command. Then, use this value to allocate a fixed-size buffer in `spi_flash_cmd_write`. Also, add a check to prevent buffer overflow problems. Finally, ensure that the `spi_flash_cmd_write_page_program` function always writes no more than 256 bytes of data when using the `spi_flash_cmd_write` function. Tested on Asrock B85M Pro4 (Winbond W25Q64FV), MRC cache still works. Change-Id: Ib630bff1b496bc276616989d4506a3c96f242e26 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-15soc/intel/broadwell/pch: Use Lynxpoint GPIO codeAngel Pons
This allows dropping `gpio.c` from Broadwell. Change-Id: I6b34e11f849cdf01e402fe79d078711af94e1ec0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50081 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15broadwell boards: Switch to Lynxpoint GPIO headersAngel Pons
Move `CROS_GPIO_DEVICE_NAME` to a new `chromeos.h` header, because Lynxpoint uses a different value. Also drop unnecessary includes. Tested with BUILD_TIMELESS=1, Google Tidus remains identical. Change-Id: I38baed2c114fb93cfb82535a6ec00fb67e596d64 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50080 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/intel/broadwell/pch: Prepare to drop `gpio.h`Angel Pons
Use `lp_gpio.h` from Lynxpoint instead. Subsequent commits will update the mainboards and then drop all GPIO code from Broadwell. Tested with BUILD_TIMELESS=1, Google Tidus remains identical. Change-Id: Idef89037c2ca781ac3e921abb4b3dc3f7c4b3b5f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50079 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/auron/var/samus: Replace define with literalAngel Pons
The `GPIO_OUT_HIGH` macro is not present on Lynxpoint headers. Change-Id: I12dd065bee49097c602febf18c6c9940ecec5106 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50078 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/jecht/var/tidus: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Tidus remains identical. Change-Id: I1521a51455e2aa148298853bb1878e82b9f0c368 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50077 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/jecht/var/rikku: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Rikku remains identical. Change-Id: I4d5bec4ec18b645a14d21fbee7334761901a30df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50076 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/jecht/var/jecht: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Jecht remains identical. Change-Id: I193fe1471b8ade5d03e874f92425962c1ed960c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50075 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/jecht/var/guado: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Guado remains identical. Change-Id: I3a806d07b0ca147492b90feaf90235ed919b1bb2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50074 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/auron/var/samus: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Samus remains identical. Change-Id: I465457ea8e9a9716121eacc0f6d64de463f41d89 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50073 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/auron/var/lulu: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Lulu remains identical. Change-Id: I0f0a584b3354971ee8d478fd17825e498ff3e423 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50072 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/auron/var/gandof: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Gandof remains identical. Change-Id: I168fcad7088706ca5b21f5fbf6790b13054499e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50071 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/auron/var/buddy: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Buddy remains identical. Change-Id: I6e6256a9cc88c9d0743150bfdf12b1b482fe157d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50070 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/auron/var/auron_yuna: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Auron Yuna remains identical. Change-Id: I17e6bf20114f43da2897ec320ca26d8c6f6a4b09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50069 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/auron/var/auron_paine: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Auron Paine remains identical. Change-Id: I00b9184fe6f002c3e089c9fbc815862d60e7694f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50068 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/intel/wtm2: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Intel WTM2 remains identical. Change-Id: I422421cc3c336a7a1aceaff7b37ab7c82f64a03f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50067 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/purism/librem_bdw: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I573cd439e8284d84036e71615944f7a195155593 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50066 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/brya: Add EC I/O decode windowsTim Wawrzynczak
BUG=b:180013349 TEST=console shows successful EC <-> SoC communications Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie09dcfa8b0de2706ffc236a978dc159594e327c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-15mb/google/brya: Enable cr50 supportTim Wawrzynczak
Add Kconfig options and devicetree entries for cr50 TPM. BUG=b:180017621 TEST=verify (via console) successful cr50 communications in verstage and payload (depthcharge). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I80e27d0377960fb81f9149efb6f062d06432d40d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-15mb/google/guybrush: Configure non-native function GPIOsMathew King
Second pass GPIO configuration to enable the non-native function GPIOs based on the guybrush Proto 0 reference schematic 0210. BUG=b:177909472 TEST=builds Change-Id: I0fdc4d7369353f88cf05e2e1ec08898d4605e602 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-15soc/amd/cezanne: Add uart.c to smm so we can support DEBUG_SMIRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ife43352db564654ed538383a157431ee10856518 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-15nb/intel/sandybridge: Correct description of QCLKAngel Pons
QCLK means "quadrature clock", and is equivalent to one half of a full clock cycle (tCK). Fix the comment. The `QCLK_PI` value is still valid. Change-Id: I7089fc32381addc280a71761a377075f107b5c62 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49363 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/intel/*: Move prmrr_core_configurePatrick Rudolph
Move prmrr_core_configure before clearing MCEs. This is required for the following patch in order to update microcode after PRMRR has been configured, but before MCEs have been cleared. According to Document 565432 this should be no issue in regards to SGX activation. Change-Id: Id2808a3989adff493aaf4175cbeccd080efaaedf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-15sb/intel/lynxpoint: Clean up lp_gpio.hAngel Pons
Move `mainboard_gpio_map` declaration inside header and reorder some function declarations. This is to align the header with Broadwell. Change-Id: I436d7fdabf8d574e5dd2787fb6097f384cc8e453 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50065 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/intel/broadwell/pch: Rename GPIO identifiersAngel Pons
Rename structs, types and functions to match Lynx Point's names. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I11ea27b00b5820eb5553712e0420836470ec0d27 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50064 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15intel/xeon_sp/util: Use get_stack_busno instead of get_cpubusnosMaxim Polyakov
This function is more convenient to get the value of a single bus number than get_cpubusnos(). Now get_cpubusnos is not used anywhere, so remove it. Change-Id: I71c06c2d69344d97e48609e67a3966ed8c671152 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-15tint: update the patch version numbers according to a new tint versionMike Banon
Rebase the libpayload_tint.patch to update its internal version numbers from 0.04+nmu1 to 0.05. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I91f780f80026147c3c35330625a4106c65a1ddf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50468 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/picasso: always include PSP secure OS in amdfwFelix Held
When USE_PSPSECUREOS isn't selected, we get stuck in FSP-S. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I60d0e5ab0bd9f4d76cc48d08ca05d27c60e898c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-14arch/x86: Drop `cstates` pointer from CPU driversAngel Pons
Nothing uses this pointer anymore. Change-Id: Id2dee8f4cb243114d6f7f7485402acb9b73b7900 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49808 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14cpu/intel/haswell: Constify ACPI c-state arraysAngel Pons
Change-Id: I5538d8279392238e59aba99ade4b5fe13f250ca8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49805 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14cpu/intel/haswell: Drop c-state table indirectionAngel Pons
Accessing it directly allows proper bounds-checking. Change-Id: Ifb539051e4a91ddcdb5ffec4850dc2fb30482aea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49804 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14cpu/intel/model_206ax: Drop c-state table indirectionAngel Pons
Accessing it directly allows proper bounds-checking. Change-Id: I2582a7edf5fba28febe570bddccacb85a3269684 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49801 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14cpu/intel/model_206ax: Replace `generate_cstate_entries`Angel Pons
Leverage the existing `acpigen_write_CST_package` function. Yes, bad devicetree values can trigger undefined behavior. The old code already had this issue, and will be addressed in subsequent commits. Change-Id: Icec5431987d91242930efcea0c8ea4e3df3182fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49093 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/cezanne: add partial data fabric setupFelix Held
I'm not 100% sure yet if this code will be common for all AMD SoCs, so I'll add a copy for Cezanne for now. This part of the code should probably be reworked after the initial bringup of Cezanne anyway. DF MMIO register configuration at the beginning of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 a3 fc00 febf 1 a3 1000000 fffcffff 2 a3 d000 f7ff 3 a0 0 0 4 a3 fed0 fed0 5 a0 0 0 6 a0 0 0 7 a0 0 0 DF MMIO register configuration at the end of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 a3 fc00 febf 1 a3 1000000 fffcffff 2 a3 d000 f7ff 3 10a3 fed0 fedf 4 a0 0 0 5 a0 0 0 6 a0 0 0 7 a0 0 0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia243a0cad311eb210d14d6242c52f599db22515c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50624 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/cezanne/include/iomap: add HPET base addressFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I72559147a3f86f0cb843b74af9b148d23229ff14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50623 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/common/block/data_fabric: add data_fabric_print_mmio_confFelix Held
Output on Picasso at the beginning of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 93 fc00 febf 1 93 1000000 ffffffff 2 93 d000 f7ff 3 90 0 0 4 93 fed0 fed0 5 90 0 0 6 90 0 0 7 90 0 0 Output on Picasso at the end of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 93 fc00 febf 1 93 1000000 ffffffff 2 93 d000 f7ff 3 1093 fed0 fedf 4 90 0 0 5 90 0 0 6 90 0 0 7 90 0 0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I74617dfc6099489f3c81d0e385b502f1bbecea78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50640 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14sb/amd/cimx/sb800: Move common OSFL method in ASLKyösti Mälkki
We deal with mb/lippert/frontrunner-af later since it currently does not include <cimx/sb800/acpi/fch.asl>. Change-Id: I30b611fc1fb01777223d7222adc96308a247a35c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50591 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14AGESA,binaryPI boards: Drop OSV in ASLKyösti Mälkki
Not referenced anywhere in ASL. Change-Id: I52ac4722e48e1cc377386316dc034fb45a98181a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50471 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14ACPI: Move common _PIC methodKyösti Mälkki
Change-Id: I659835354570fb1d4860fcbddf2a51831170a374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14sb,soc/amd: Drop empty CIRQ call from _PICKyösti Mälkki
Change-Id: Iaa51e0530a3f72456d3d4e7a0c55b768ba63e322 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49904 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14sb/amd/cimx/sb800: Drop CIRQ method from _PICKyösti Mälkki
Change-Id: Ie4aad7b6580100377c12f128905f7f409bdb5295 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50590 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14util/cbfstool: Fix build in 32-bit userspaceKyösti Mälkki
Fix regression from commit 0dcc0662f3 util/cbfstool: Introduce concept of mmap_window. Use of region_end() wraps around at 4 GiB, if utility is run in 32bit userspace. The build completes with an invalid coreboot.rom, while one can find error message in stdout or make.log: E: Host address(ffc002e4) not in any mmap window! Change-Id: Ib9b6b60c7b5031122901aabad7b3aa8d59f1bc68 Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-14soc/amd/picasso/data_fabric: factor out common MMIO register definesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I663a73308d33f48c6b945007f3eaac84d4712f59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50639 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/picasso/data_fabric: move more helper functions to common codeFelix Held
The number of data fabric MMIO registers is SoC-specific, so we need to keep that in the SoC code. This also removes a redundant pair of brackets and moves a loop counter declaration into the head of the loop. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8499f1c1f7bf6849b5955a463de2e06962d5de68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50638 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/picasso/data_fabric: use common access functionsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8cda860ca0ff81d7703c3277aeec629d89eab45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50622 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/common/block/data_fabric: add data_fabric_broadcast_read/write32Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81e7ff293865ef22ed74606e1e79f67a460de4a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50621 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/common/block/data_fabric: add data_fabric_write32Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9c1ae03e9aec1dec45333e697060308cb6cbda4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/50620 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/picasso: move data_fabric_read32 to common codeFelix Held
The exact same mechanism is used on Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3179d8ec35efa29f9bc66854c3690b389d980bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/50619 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14sb,soc/amd: Move _PIC method to global scopeKyösti Mälkki
Fix regression with commit aa969e887a ACPI: Move PICM declaration. While mentioned in the commit message there already, the default value for AMD boards changed from IOAPIC mode to PIC mode. ACPI 6.3 spec has this text regarding _PIC method: If the platform CPU architecture supports PIC mode and the method is never called, the platform runtime firmware must assume PIC mode. If MADT has IOAPIC entries, OS will want to change to APIC model. But the method _PIC was not in the global scope so it could not be called and therefore _PRT continued to report PIC model interrupt routing. Already fixed for soc/amd/picasso in commit 839f668. Change-Id: I7f3bb0d45946cec315694de1d540fea4d828348e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-14soc/amd/cezanne/chipset.cb: add SMBus and data fabric PCI devicesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ica9b4adb1ec2b3663ce2d623cfe7b6539cd9c71b Reviewed-on: https://review.coreboot.org/c/coreboot/+/50631 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/cezanne: move CPU cluster to chipset device treeFelix Held
This will be common for all boards, so move it to the chipset device tree. TEST=CPU cluster and LAPIC still show up in console logs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia49e7b4cfc09c60b6152b8ccc47f37b6adc1e319 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50613 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14mb/amd/majolica/mainboard: Set ACPI IRQRaul E Rangel
We now pass the ACPI SCI IRQ to the OS, so make sure the board routes it correctly. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1b4d5e0bfb1d9df9ac8a8c41cdf466a67f2673d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-02-14soc/amd/cezanne: Fill FADT and MADTRaul E Rangel
The MADT doesn't populate the IO-APICs yet since we need FSP to configure those. The FADT differs from picasso in the following ways: * The duty_offset is supposed to be 0 * Don't clear x_firmware_ctl_l * Make the extended addresses use MMIO Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14soc/amd/cezanne: Enable uCode updateRaul E Rangel
TEST=Boot majolica and see microcode update CBFS: Found 'cpu_microcode_blob.bin' @0x6900 size 0x15c0 in mcache @0xcf7fe9d8 microcode: patch id to apply = 0x0a50000b microcode: being updated to patch id = 0x0a50000b succeeded Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If50b1d8b3ebf4b3e6f8a9dd3ab96073e0cb92424 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14soc/amd: Move update_microcode.c to common/block/cpuRaul E Rangel
We also want to support uCode loading on cezanne. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-13superio/smsc/sch5545: Add missing <types.h>Elyes HAOUAS
Add needed but missing <types.h>. Change-Id: I16c6a86e8c8863a8e16a63a379484c2b47d5185e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-13include/acpi/acpi.h: Add ACPI_MADT_LAPIC_NMI_ALL_PROCESSORSRaul E Rangel
This is a magic value that means all processors. See Table 5-52 Local APIC NMI Structure in ACPI Spec 6.3. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic2fc060fda21bec44258bcae62ddb230be542759 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13soc/amd/cezanne: select ACPI support and make the compiler happyFelix Held
Follow-up patches will add more functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13soc/amd/common/acpi/gpio_bank_lib.asl: Add missing headerRaul E Rangel
This file references ACPIMMIO_GPIO0_BASE. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic65a1f8759d10e7d78e30cfc82895e5af8cd83a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50571 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13mb/google/guybrush: Add plain dsdtRaul E Rangel
Needed to enable ACPI support for cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia5869905ed053cdca5f61697cffc7f9b59370859 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13mb/amd/majolica: Add plain dsdtRaul E Rangel
Needed to enable ACPI support for cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifd71635d3493e0cf104b60ecf94ebdf70d512b94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13soc/amd/cezanne/acpi: Add plain soc.aslRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I227cdb7cb4848d1d26f6d7fa13ac2cc1aea08d1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13soc/amd: introduce and use common IOAPIC IDsFelix Held
Stoneyridge used CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 directly as IOAPIC IDs and Picasso had Kconfig options to configure that, but still used the common SMBus controller code that used CONFIG_MAX_CPUS as ID for the FCH IOAPIC. If a board overrides the PICASSO_FCH_IOAPIC_ID Kconfig option to a value that isn't CONFIG_MAX_CPUS, we'll get a mismatch between the ID that gets written into the FCH IOAPIC register and the ID in the corresponding ACPI table. In order to avoid that add defines to each SOC's southbridge.c and use them in all soc/amd code. Change-Id: I94f54d3e6d284391ae6ecad00a76de18dcdd4669 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50575 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13soc/amd/cezanne: always include PSP secure OS in amdfwFelix Held
When USE_PSPSECUREOS isn't selected, we don't even get post codes on Majolica, so remove this option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0ec976f40d962a2d9f2bd36dc97d86526bd661ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/50601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 11:34:13 +0000