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2023-01-22soc/intel/{adl,mtl,tgl}: change selection for ↵Matt DeVillier
DEFAULT_SOFTWARE_CONNECTION_MANAGER Needs to be selected for ChromeOS mainboards even for non-ChromeOS builds, else Thunderbolt/USB4 doesn't work under Windows (and likely Linux as well). TEST=build/boot Windows on drobit/banshee, verify TB functional Change-Id: Iee3f99840f0c6cc384d9fdef6dff55bcbfc0380f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72140 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22intel/common/block: Fix potential buffer overflowBora Guvendik
Possible Buffer Overflow - Array Index Out of Bounds. Array regions size is 256 but 'i' iterates from 0 to 256. Found-by: Klockwork BUG=None BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iee45a5821b9dd3f9e6f9816599beebf34555426d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72049 Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/amd/stoneyridge: clean up global NVSFelix Held
Remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b172214998818f841f5694f47815eddfaf9deaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/72139 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/amd/picasso: clean up global NVSFelix Held
Remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I79509146431e4584e50af4477f3f50dc3cf01bcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72138 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22Revert "mb/google/brya: Add EC mux device to brya0"Anil Kumar
This reverts commit 197d550d069f918698fa7cd8dda73e09fbfda30c. Reason for revert: breaks TBT and TypeC display on Brya0 Bug=265375098 Branch=firmware-brya-14505.B Test=Build and boot Skolas board with Brya0 image. Test TBT and TypeC display functionality. Change-Id: Ia0283b023949476e90edff7151d605fa36331bfd Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72081 Reviewed-by: Prashant Malani <pmalani@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-22soc/intel/apollolake: Add PMC macros for common code usageSubrata Banik
This patch adds new macros (i.e. SUS Power Failure and Power Failure) from the APL EDS vol 1 (doc 569262) to be able to implement common code API to clear the power failure status bits. Note: as per the EDS those newly added power management failure bits are RO and shouldn't change any functionality of the existing APL SoC code. The reason behind adding those macro definitions is to fix the compilation issue due to code change targeted for the Intel SKL and Xeon-SP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0bbf11ada2b2f8735173be69ad157b8055021126 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72130 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/intel/denverton_ns: Add PMC macros for common code usageSubrata Banik
This patch adds new macros (i.e. SUS Power Failure and Power Failure) from the DNV EDS vol (doc 558579) to be able to implement common code API to clear the power failure status bits. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6ed962eae79154a8faea382dbe8367133cb05eda Reviewed-on: https://review.coreboot.org/c/coreboot/+/72134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-22mb/siemens/mc_apl1/var/mc_apl6: Enable early POSTJan Samek
Enable early POST code display on this variant using the common mc_apl1 baseboard functionality. BUG=none TEST=Boot on mc_apl6 and observe that POST codes are displayed before DRAM training. Change-Id: I2a52c241c383f8ebcf05052e9bc0ba13e63e3728 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-22mb/siemens/mc_apl1: Move POST logic to mainboard levelJan Samek
Move logic previously used only in the mc_apl2 variant to the mainboard level so that other variants can also make use of it without code duplication. This functionality on the mc_apl6 variant will be enabled in a follow-up patch. BUG=none TEST=Boot on siemens/mc_apl2 and observe that the POST codes are displayed before DRAM training. Change-Id: I762e328ad06c047d911ce1fc40f12a66cbd14e11 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-21nb/amd/pi/Kconfig: Remove unused CONSOLE_VGA_MULTIElyes Haouas
Change-Id: I93455f38663cf29d8b5160ac21c94db08eb44fa9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-21sb/amd/pi/hudson/Kconfig: Remove unused AZ_PINElyes Haouas
Change-Id: I1542c5662162e919752c334baa9c31cddc5036af Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-21arch/x86/Kconfig: Remove unused NUM_IPI_STARTSElyes Haouas
Change-Id: I3b781c42ef6c23a5dcd31215c14fb9d7104822f2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-21arch/x86/include: Remove unused <stddef.h>Elyes Haouas
Change-Id: I2a4b00d06c92eea1b83002c69d93037f84592393 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72111 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-21sb/amd/pi/hudson/Kconfig: Remove AHCI_ROM_FILEElyes Haouas
Remove AHCI_ROM_FILE since it's not used and there is no ahci.bin file. Change-Id: I008c6ac78957500d4ce301fe70f5b6d4a549b573 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-21soc/intel/baytrail: Fix indentation for the PMC (pm.h) macrosElyes Haouas
This patch fixes the alignment of the PMC macros defined in the pm.h file. Change-Id: Ib5ff87e2f6524ca1be69027080149a3fbe2df7d9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72158 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-21soc/intel/braswell: Fix indentation for the PMC (pm.h) macrosElyes Haouas
This patch fixes the alignment of the PMC macros defined in the pm.h file. Change-Id: I9a55e1b099a53180e40eedcc52120d65558e7f8b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72157 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-21soc/intel/apollolake: Fix indentation for the PMC (pm.h) macrosSubrata Banik
This patch fixes the alignment of the PMC macros defined in the pm.h file. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia8d35a5d104658b7900fde7f7b8c6f88530a614e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72129 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20mb/google/brya/acpi: Update NVPCF_FUNC_UPDATE_DYNAMIC_PARAMSTarun Tuli
1) Update location of TGP (MAGA) to Params2[15:0] 2) Add TPPA (value of 25W) Package: ... Case (0x02) { Local0 = Buffer (0x31) { 0x22, 0x05, 0x10, 0x1C, 0x01 } CreateWordField (Local0, 0x1D, MAGA) CreateWordField (Local0, 0x19, TPPA) CreateDWordField (Local0, 0x15, CEO0) MAGA = 0x50 TPPA = 0xC8 CEO0 = 0x0200 Return (Local0) } ... BUG=b:214581372 TEST=build and verify DSDT on device Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I69b80f4af2ecef6cf91034fc15fb6e8715eeca4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69639 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20mb/google/skyrim/var/frostflow: Update I2C setting for touchpadRex Chou
Update setting for touchpad I2C frequency and hold time to meet touchpad i2c SPEC. - Frequency: 380 ~ 400 kHz - hold time : 0.3 ~ 0.9 us BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 393.7 kHz Hold time = 0.604 us Change-Id: Iecf4960a12aa56ac307fb9022e47c4e94a2551c1 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72114 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/glinda,mendocino,phoenix/espi_util: add comment about registerFelix Held
Even though the register name begins with ESPI, it resides in the SPI registers and not in the eSPI registers, so add a comment to point this out to hopefully avoid some confusion. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9f8d15ceb98f51aad0816021f98ec5c78953e7f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-20soc/amd/glinda/espi_util: update file to match documentationFelix Held
Checked against document #57396 revision 1.52 and removed the DIS_ESPI_MASCTL_REG_WR define, since that bit is marked as reserved. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3e8b1c65118b4e85e7934e822a7a7e329746a88d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-20soc/amd/phoenix/espi_util: remove TODO after checkingFelix Held
Checked against both documents #57019 revision 1.59 and #57396 revision 1.50 that the definitions and the code still apply to Phoenix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id65301ec730793f41044696f2e99356f2e899137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-20soc/amd/glinda: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie1c3c25591deadb27b7bf38a81dcd6fe746de55b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72096 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/phoenix: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5a9b0a24f57a81b98c7553517fe5f25ff63c5316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72095 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/mendocino: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I884d6a7dedb73028f8942fdda86b0c9910fa996a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72094 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/cezanne: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4034e959d167fb1e08ee5b15e21fb93bc89db8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72093 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/mendocino/acpi/pci_int_defs: remove TODO after checkingFelix Held
All field definitions in the IndexField object match both the info in the PPR #57243 revision 3.02 and also match the defines in soc/amd/ mendocino/include/soc/amd_pci_int_defs.h. The IndexFieldvonly defines the subset of the IRQ mapping registers that are used or likely needed in the future. This is handled in the same way for the other AMD SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b0adfecc99945de69b4853f4423b4c10951d3e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72092 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/intel/*/include/soc/gpio.h: Add "IWYU pragma: export" commentElyes Haouas
Change-Id: If44a07503470f57037b59d03eea830703a3c604a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72100 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20mb/siemens: Unify and clean lcd_panel.c coding styleJan Samek
With the addition of the mc_ehl3 board variant, a few points about commenting the code arose either from the review or during the implementation itself. This patch unifies structure of these files, which have a similar structure across more Siemens boards utilizing the PTN3460 eDP-to-LVDS bridge. BUG=none TEST=Check that images for the affected boards can be built. Change-Id: I59820362e1f87e296c5548b9c3cecba4d2710fe7 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72068 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20mb/siemens/mc_ehl3: Add PTN3460 eDP-to-LVDS bridgeJan Samek
This board contains in addition to its base variant, mc_ehl2, an LCD panel driven through the PTN3460 eDP-to-LVDS bridge. This patch enables the PTN3460 support by adding the device to devicetree.cb and board-specific configuration parameters in lcd_panel.c, based upon a similar implementation in siemens/mc_apl7. BUG=none TEST=Boot with the LCD panel attached and observe whether the picture is stable and free of artifacts coming from wrong resolution, timing etc. Change-Id: Ib8a1a6f47053406e42554c2dd33684165d54be08 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-20mb/google/brya/var/gaelin: Add touch panel module settingMike Shih
1. Enable multiple GPIOs to support the touch panel. 2. Add I2C setting for touch panel. BUG=b:260818082, b:264812909 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Change-Id: I2b805d1960f8b4e3e27f1af02f9c4d31f973288f Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-01-20soc/amd/mendocino: Remove TODO after reviewFred Reitberger
Remove TODO comment after reviewing against mendocino ppr #57243, rev 3.00 BUG=b:263563246 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9a89751df71eb32b2c8d99c568341dd669b5f065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72073 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/intel: Remove unused <stddef.h>Elyes Haouas
Change-Id: I8432d799c9bf23058b7b903bb07f6c2b4308eeba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72103 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20drivers/intel/gma/hires_fb/gma-gfx_init.adb: Remove spaces before tabsElyes Haouas
Change-Id: Ifab3fcd2de8f0c1672d1a9a21c8e0c5dba5b7443 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72077 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-20soc/intel/common/block/fast_spi/Makefile.inc: Remove spaces before tabsElyes Haouas
Change-Id: Id2b408e24f74367777b1b949623d6692f2f19e6d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72076 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-20mb/intel/adlrvp/spd/Makefile.inc: Remove spaces before tabsElyes Haouas
Change-Id: I7bd29bab2c77da2ffe86167d54e87c9941355ea7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-20drivers/intel/gma/text_fb/gma-gfx_init.adb: Remove spaces before tabsElyes Haouas
Change-Id: I421602c81d9a186eb36a289d6e5048b5aa343a2d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-19mb/siemens/mc_ehl3: Use device/mmio.h instead of device/pci_ops.hJan Samek
The {read,write}{16,32}() functions used in this file come from the mmio.h header, so include it directly. BUG=none TEST=Read out the SD card controller (device 1a.1) PCI registers in Linux and check whether the values reflect the ones defined in this file. Change-Id: Iff7b55ef2bf98371b7d7d9114ccf3ebed64772a2 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72009 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-19soc/amd/stoneyridge/northbridge: use acpi_align_currentFelix Held
Use acpi_align_current to align the ACPI tables on a 16 byte boundary. This changes the alignment of the HEST, IVRS, SRAT and SLIT tables from 8 bytes to 16 bytes. The alignment of the ALIB and PSTATE SSDT tables was already 16 bytes before, so the alignment of those isn't changed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8933e3731b67012bcae0773db2f7f8de7cd31b56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72055 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19intel/meteorlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for ChromeOS platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Iaba1ea29a92a63d2b287e1ccdea1a81ec07b9971 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19soc/intel/meteorlake: Increase cbmem buffer size for the debug imageKapil Porwal
Currently most of the FSP debug messages (when enabled) are truncated due to insufficient size of cbmem buffer. Increase premem cbmem console size to 0x16000 bytes and cbmem buffer size to 0x100000 bytes so that cbmem buffer can contain most of the debug logs when FSP debug messages are enabled. BUG=b:265683565 TEST=Verify output of 'cbmem -c' when FSP debug messages are enabled but MRC debug message. Note: Still 350/2200 lines of premem messages are missing. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I120423e1dd2bc468cf9cec6da1246ac3c0a155e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72048 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19soc/intel/meteorlake: Increase cbmem buffer size to 256KBKapil Porwal
Current size of the cbmem buffer (128KB) is insufficient to contain the complete debug logs which is more than 166KB hence, cbmem console buffer has wound off to contain the maximum possible debug messages within the allocated buffer as results, we are seeing truncated debug message while looking into the cbmem console. This patch increases cbmem buffer size to 256KB so that the complete debug log can be stored in it. BUG=b:265683565 TEST=Make sure that logs from all the boot stages can be seen using 'cbmem -c'. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ibeabb61d60491b831252b7161c9d3181fbe09e73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72047 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19mb/google/skyrim/var/frostflow: set dxio_tx_vboost_enableFrank Wu
Turn on the dxio_tx_vboost_enable for frostflow in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259007881, b:248221908 BRANCH=none TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iaac331737c83ac7a4a1261c32151359e126a009e Reviewed-on: https://review.coreboot.org/c/coreboot/+/71926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per portKane Chen
This patch supports projects to use _DSM to control USB3 U1/U2 transition per port. More details can be found in https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm- The ACPI and USB driver of linux kernel need corresponding functions to support this feature. Please see https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm BUG=b:253402457 TEST=tested on felwinter and found _DSM method is created. Change-Id: Iffb2498e26352a3f120c097c50587324e311e8ba Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71924 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19soc/mediatek/mt8188: Allow SSPM to access PWRAP interfaceSen Chu
Allow SSPM to access PWRAP interface. BUG=b:254566089 TEST=build pass and boot to OS. Change-Id: I4b134983dcde1cc293f4b798f91b997baf96d299 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-01-19tree: Drop Intel Ice Lake supportFelix Singer
Intel Ice Lake is unmaintained and the only user of this platform ever was the Intel CRB (Customer Reference Board). As it looks like, it was never ready for production as only engineering sample CPUIDs are supported. As announced in the 4.19 release notes, remove support for Intel Icelake code and move any maintenance on the 4.19 branch. This affects the following components and their related code: * Intel Ice Lake SoC * Intel Ice Lake CRB mainboard * Documentation Change-Id: Ia796d4dc217bbcc3bbd9522809ccff5a46938094 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72008 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19mb/google/skyrim/var/markarth: set dxio_tx_vboost_enableFrank Wu
Turn on the dxio_tx_vboost_enable for markarth in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:263534907, b:263216451 BRANCH=none TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I0798c1d9788e1911c2643bf387722b072aa79045 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-01-18mb/siemens/mc_ehl: Remove '_' from mc_ehl3 part numberJan Samek
Change MAINBOARD_PART_NUMBER Kconfig value for mc_ehl3 from "MC_EHL3" to "MC EHL3". Change-Id: Ie548607c5fb62faaed4921af714bc9b912e558a8 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71775 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18vc/siemens/hwilib: Use 3rd person singular in commentPaul Menzel
Change-Id: I1d9d123d2a29178541ab24c70ba529f6bfa2b6c8 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-18vc/siemens/hwilib: Rename 'maxlen' to 'dstsize'Werner Zeh
The parameter 'maxlen' can be a bit confusing as it actually is referring to the size of the destination memory block where the requested parameter is stored to. Rename it to 'dstsize' and change the type to size_t to be more clear here. In addition, add a comment line for this parameter in the description of the function 'hwilib_get_field()'. This patch has no impact to the generated binary (checked with timeless build). Change-Id: I572dc0f3ff3d0c177d608332a88991396b82c2fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72045 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-01-18Documentation: Update list of boards supported by vbootMartin Roth
This is the list generated by util/vboot_list/vboot_list.sh Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib782a676fed312a2c84e89914f871984a289f610 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72003 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18mb/google/brya/var/marasov: Remove wlan RTD3 supportFrank Chu
Wlan power enable pin is changed from EN_PP3300_WLAN to SLP_SUS_L. Remove unused RTD3 driver. BUG=b:263448873 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I22448a8cb28ddadb93b114c096e364980feab6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71693 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18mb/google/skyrim: Add custom amdfw.cfg file to remove fwTPMMartin Roth
Skyrim doesn't use the firmware TPM, so remove the binary from the image. Note that because this was not used, removing it doesn't change the boot time. BUG=None TEST=Boot Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia627b128c3346a2556c5306de7506519d1f2d70c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18vc/siemens/hwilib: Fix coding styleWerner Zeh
As per the code style there is no space before the opening brace of a function declaration. Delete the space in hwilib.c and hwilib.h. Change-Id: Ie122ccd2dbae97f595463a097826d3415718a8bc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72044 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/amd/common/block/acpi/cppc: drop outdated commentFelix Held
Since commit d5ab24cd4800 ("soc/amd/common/acpi/cppc: add nominal and minimum frequencies") the fields that got added in CPPC version 3 get populated, so remove the now outdated comment about the fields added in version 3 always being set to CPPC_UNSUPPORTED. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4c975b42fc4f67329170801b871d6bbdf9637d04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-18soc/intel/alderlake: Add print that MRC training screen displayedTarun Tuli
Add a INFO print indicating that we did infact attempt to display the MRC training message to the user. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Print seen in cbmem -c Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I1a20fb221aa2fa0eeaf9b7f8cf3d8a8ab0b91133 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-01-18soc/amd/*/agesa_acpi: add TODO for adding CRAT tableFelix Held
The Picasso SoC code generates a CRAT ACPI table which is not done for Cezanne and newer. A significant part of the Picasso CRAT generation code can likely be moved to the common AMD SoC code and then used in all SoCs, but this still needs to be checked. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f1ebe74f0376c60396dbd80e64676d1374ed811 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72027 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/amd/glinda/agesa_acpi: use acpi_align_current to align IVRS & ALIBFelix Held
This changes the alignment of the IVRS table from 8 bytes to 16 bytes and aligns the ALIB table to a 16 byte boundary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I965791fbbe499702e191dcbf1f5fbfcb5e1bab6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18soc/amd/phoenix/agesa_acpi: use acpi_align_current to align IVRS & ALIBFelix Held
This changes the alignment of the IVRS table from 8 bytes to 16 bytes and aligns the ALIB table to a 16 byte boundary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I766260aefcac6876609d6b45202b41a3e9e44385 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18soc/amd/mendocino/agesa_acpi: use acpi_align_current to align IVRS&ALIBFelix Held
This changes the alignment of the IVRS table from 8 bytes to 16 bytes and aligns the ALIB table to a 16 byte boundary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2b48a7cbed84551e7651992589c38eac54f27d1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18soc/amd/cezanne/agesa_acpi: use acpi_align_current to align IVRS & ALIBFelix Held
This changes the alignment of the IVRS table from 8 bytes to 16 bytes and aligns the ALIB table to a 16 byte boundary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4de66ab11508814da5d7fb440a1083a52551bcf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18soc/amd/picasso/agesa_acpi: align ALIB with acpi_align_currentFelix Held
This makes sure that the ALIB table is aligned on a 16 byte boundary. TEST=Mandolin still boots Linux and the position and size of the ACPI tables in memory shown by dmesg hasn't changed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I90781ef98b729c0a8d1f5dde46fc9ca5d08618b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18soc/amd/picasso/agesa_acpi: use acpi_align_current to align CRAT & IVRSFelix Held
This changes the alignment of the CRAT and IVRS tables from 8 bytes to 16 bytes. TEST=Mandolin still boots Linux and the position and size of the ACPI tables in memory shown by dmesg hasn't changed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88df331c8410d8dca41a414543f051f5e4656ff1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18soc/intel/elkhartlake: Fix incorrect `prev_sleep_state` issueSubrata Banik
The patch fixes indication of incorrect `prev_sleep_state` on the next boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power failure. As a result, every early warm/global reset is considered as power failure after looking into the PMC MMIO CON-A register alone (as ignoring the ACPI PM_CTRL.WAK_STS bit). As per the code comment this code logic is expected to check the power failure reason if PCH doesn't set the WAK_STS while waking from G3 state. Without this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 5 With this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 0`. It matches with the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib43d3402f94f47dc576fb99a6b2a7acf6f0af220 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71982 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/intel/icelake: Fix incorrect `prev_sleep_state` issueSubrata Banik
The patch fixes indication of incorrect `prev_sleep_state` on the next boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power failure. As a result, every early warm/global reset is considered as power failure after looking into the PMC MMIO CON-A register alone (as ignoring the ACPI PM_CTRL.WAK_STS bit). As per the code comment this code logic is expected to check the power failure reason if PCH doesn't set the WAK_STS while waking from G3 state. TEST=Able to build and boot google/dragonegg. Without this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 5 With this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 0`. It matches with the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0e5a6e54abc7c03a2fbffa308db20c392e2a600b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71983 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/intel/jasperlake: Fix incorrect `prev_sleep_state` issueSubrata Banik
The patch fixes indication of incorrect `prev_sleep_state` on the next boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power failure. As a result, every early warm/global reset is considered as power failure after looking into the PMC MMIO CON-A register alone (as ignoring the ACPI PM_CTRL.WAK_STS bit). As per the code comment this code logic is expected to check the power failure reason if PCH doesn't set the WAK_STS while waking from G3 state. TEST=Able to build and boot google/dedede. Without this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 5 With this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 0`. It matches with the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id2c1f24a8fa54eea512b5bd3dd91423f9892687d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71984 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-18soc/intel/tigerlake: Fix incorrect `prev_sleep_state` issueSubrata Banik
The patch fixes indication of incorrect `prev_sleep_state` on the next boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power failure. As a result, every early warm/global reset is considered as power failure after looking into the PMC MMIO CON-A register alone (as ignoring the ACPI PM_CTRL.WAK_STS bit). As per the code comment this code logic is expected to check the power failure reason if PCH doesn't set the WAK_STS while waking from G3 state. TEST=Able to build and boot google/volteer. Without this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 5 With this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 0`. It matches with the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0e48b110826f16d13d18c138fce03a56c85b9d1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71985 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-18soc/intel/alderlake: Fix incorrect `prev_sleep_state` issueSubrata Banik
The patch fixes indication of incorrect `prev_sleep_state` on the next boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power failure. As a result, every early warm/global reset is considered as power failure after looking into the PMC MMIO CON-A register alone (as ignoring the ACPI PM_CTRL.WAK_STS bit). As per the code comment this code logic is expected to check the power failure reason if PCH doesn't set the WAK_STS while waking from G3 state. TEST=Able to build and boot google/taeko. Without this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 5 With this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 0`. It matches with the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I52f9c261f4eea34e6d2300c8de97ee018d886189 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71987 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/intel/meteorlake: Fix incorrect `prev_sleep_state` issueSubrata Banik
The patch fixes indication of incorrect `prev_sleep_state` on the next boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power failure. As a result, every early warm/global reset is considered as power failure after looking into the PMC MMIO CON-A register alone (as ignoring the ACPI PM_CTRL.WAK_STS bit). As per the code comment this code logic is expected to check the power failure reason if PCH doesn't set the WAK_STS while waking from G3 state. TEST=Able to build and boot google/rex. Without this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 5 With this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 0`. It matches with the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Idc40045445cccc5b34fb49901d9ef548f2f0560b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71986 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/intel/cannonlake: Fix incorrect `prev_sleep_state` issueSubrata Banik
The patch fixes indication of incorrect `prev_sleep_state` on the next boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power failure. As a result, every early warm/global reset is considered as power failure after looking into the PMC MMIO CON-A register alone (as ignoring the ACPI PM_CTRL.WAK_STS bit). As per the code comment this code logic is expected to check the power failure reason if PCH doesn't set the WAK_STS while waking from G3 state. TEST=Able to build and boot google/hatch. Without this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 5 With this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 0`. It matches with the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I05a2fab75c3d931651885db0003ab8c5748a1568 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71934 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/intel/elkhartlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I73bac9560d0ff315d6fe6f4efc3ee9011f77c660 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72036 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/intel/apollolake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Iccf37a340880e4b5a18f51c3add9a15a74e1d7b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72030 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/intel/braswell: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes alphabetic ordering of included headers. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I55fa5941a9255f60c2aa23b90d16cf342d6f458f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72032 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-18soc/intel/jasperlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes alphabetic ordering of included headers. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: If069e66f2762eb373d35d635c09226ac5be99c7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72039 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-18soc/intel/skylake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes alphabetic ordering of included headers. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I02fe236506abbc0d97982747cfcf3c0e9ef4897a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72040 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-18soc/intel/xeon_sp: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes alphabetic ordering of included headers. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I8135dc918cb04c854dc003966b7657806a42bad9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72042 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-18soc/intel/tigerlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes alphabetic ordering of included headers. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I12497d46e58aae41ec8dcb5d567267579dc12fc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72041 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/intel/cannonlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes alphabetic ordering of included headers. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I349a2b24ecdee347548b5c7b292c5075e6150a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72033 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-18soc/amd: Include <gpio.h> instead of <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: I112e41ad4c7ee638954dfe3f1ddfeb10c138459a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-17soc/amd: introduce and use common amd_cpu_bus_ops structFelix Held
The device operations for the CPU bus are identical for all AMD SoCs, so introduce a common device operations struct for this and use it in all AMD SoC's chipset devicetrees as ops for the CPU cluster. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id32f89b8a33db8dbb747b917eeac3009fbae6631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-17soc/intel/meteorlake: Avoid redundant chipset programming in romstageSubrata Banik
This patch refactors the mainboard_romstage_entry() function to avoid redundant chipset programming caused by global reset due to CSE FW sync operation. Hence, keeping only the minimal and mandatory operations required to perform CSE FW sync successfully. This would help to optimize the boot flow by removing redundant programming like SA, SMBUS twice in every CSE FW update path. TEST=Able to build and boot Google/Rex successfully. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1a13fac1e99341991d8dd818d4ab8a20d209a94c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71933 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17soc/intel/alderlake: Avoid redundant chipset programming in romstageSubrata Banik
This patch refactors the mainboard_romstage_entry() function to avoid redundant chipset programming caused by global reset due to CSE FW sync operation. Hence, keeping only the minimal and mandatory operations required to perform CSE FW sync successfully. This would help to optimize the boot flow by removing redundant programming like SA, SMBUS twice in every CSE FW update path. TEST=Able to build and boot Google/Marasov successfully. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iba9767ef51d7fc7ecf9de14454105865433ba041 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71932 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17soc/amd: Use fixed EFS location for Phoenix & GlindaMartin Roth
The AMD SoCs no longer have a variable position for EFS - it's now fixed at 0xff020000 - 128KiB into the 16MiB ROM decode region. It's a little more complex than that because the chip can be larger than 16MiB, and the entire ROM can be decoded if mapped above the 4GiB boundary, but we don't currently support doing that in coreboot, so this is enough for now. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I343a875ba9aa8294a090f2eff7b5dfb5e86334f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-17payloads/*/Kconfig.name: update documentation linkEvgeny Zinoviev
Old wiki is outdated for years but Kconfig help messages of some payloads still reference it. This commit changes those links to the corresponding page at doc.coreboot.org. Change-Id: I81653f1b010d8a3ac4dfc4c6ad4fa714ce5d59a1 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-17mb/google/skyrim: Set winterhold SPI fast read speed to 100MHzMartin Roth
Winterhold runs with the SPI fast read speed set to 100MHz. This decreases boot time by roughly 100ms. BUG=None TEST=Examine boot times. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I879e17fb0212910c7f90ba0e78ee16bea8b7cffa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-17soc/intel/meteorlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KBSubrata Banik
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix cbmem buffer overflow issue. BUG=b:261800015 Test=Boot MTL simics and check cbmem -c | grep 'CBFS: Found' lists all stages. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6a49f88aff07841d105cd3916086aa9e496654c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71921 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17mb/google/marasov: Skip MBP HOB creation to save boot timeSubrata Banik
This change skips the MBP HOB creation since coreboot doesn't use it and also helps to reduce the boot time by ~10msec. Boot time data: Before: * 955:returning from FspSiliconInit 897,278 (33,603) After: * 955:returning from FspSiliconInit 864,543 (21,273) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia97cca560869fcfd55e65c2e1719cceec6f3ab7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71873 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17treewide: Fix old-style declarationsElyes Haouas
Replace old style declaration "const static" with "static const". This to enable "Wold-style-declaration" command option. Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-17Documentation: Add 4.20 release notes template and update indexMartin Roth
Also update Month abbreviations to full month names. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I99c1a037c0fc3d0cfec6464956f4263debdfccd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71941 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17Documentation/releases: Finalize the 4.19 release notesMartin Roth
These are the final 4.19 release notes before tagging the release. Final updates to statistics and removal of comments saying "planned" and "Upcoming" will be removed after the release is tagged. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie20ad22732ce2e1d92e47b8e48268c6a5a34ca5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71942 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17mb/starlabs/starbook/adl: Fix alignmentSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4a3f871f2418438ef8e780a39935dfa2f86d8dbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71895 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-16soc/amd/picasso/include/acpi: introduce and use ACPI_SCI_IRQ definitionFelix Held
The newer AMD SoCs define ACPI_SCI_IRQ in the SoC's acpi.h header file and use this definition in the mainboard code, so port this back to Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib569747aa388d7953e79de747905fb52c2a05e74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-16Revert "mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPD"Martin L Roth
This reverts commit 0e945a3426782e3c054a920ff8be3cd865f697ba. Reason for revert: Breaks build. Need to be merged after https://review.coreboot.org/c/coreboot/+/71715 which adds the register that this patch enables Signed-off-by: Martin L Roth <gaumless@gmail.com> Change-Id: I0ac3fb1a44e23e19c9711287f3a6a8402a6ffd79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71283 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-16Revert ".gitmodules: Fix submodule revision to v0.1 tag"Maximilian Brune
This reverts commit 59a1a30ae1555e654b07f7ec7d76798bc408908f. git submodule updates currently break, since apparently you can't use git tags in the .gitmodules file. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ibbc2bee21a723bd6d602ca435cada1dc0da03091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-16mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPDSean Rhodes
Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id53c9a6495d584c374e89b76d1fd4258654b6f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-01-16commonlib/storage: Add common eMMC functionsShelley Chen
Now that multiple platforms are trying to initialize eMMC in coreboot instead of depthcharge, lets move common functionality into commonlib instead of copying the same functionality between multiple platforms. Note for consistency, changed name of set_early_mmc_wake_status() to mmc_set_early_wake_status(). Also adding an mmc_send_cmd1() function for retrieving the Operating Conditions Register (OCR) contents. BUG=b:218406702 BRANCH=None TEST=emerge-herobrine coreboot chromeos-bootimage flash onto villager device and make sure still boots ChromeOS Change-Id: Id00535b05bbd379081712601ef10e762c1831747 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15util/kconfig: Add comment explaining difference from upstreamNicholas Chin
coreboot adds a patch on top of upstream Kconfig which allows the generated Kconfig dependency files to be placed in a separate directory than the autoconfig files based on the KCONFIG_SPLITCONFIG variable. Add a comment to explain this difference. Change-Id: Ief38ab84f852ff24f896ec8bbf094aa737a172d9 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15util/kconfig: Fix patch to be compatible with quiltNicholas Chin
The patch added in commit b7f92a0b6a0f (util/kconfig: Add patch to move Kconfig deps to build/config) uses git diff formatting, which is incompatible with quilt. Change-Id: I95bfe6571e3a2cc2b38074b4338f1610a4c8a595 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15mb/bostentech: Update name in KconfigMartin Roth
The Bostentech mainboard appears out of order - this can be fixed either by renaming the mainboard to start with S, or by the simpler method used here by putting the mainboard directory name as the main name, then noting that the full name is "Shenzhen Bostrontium Teng Technology". Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I31b4c663b68cdcde2d175f080f011f2998e56074 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-15soc/intel/apollolake/pmutil.c: Fix smi_sts_bits[HSMBUS_SMI_STS_BIT]Elyes Haouas
Found using -Woverride-init command option. Change-Id: I9f0755de9fae678fc5d78a709453fd1098d70e50 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com>