diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-01-19 17:48:44 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-20 16:51:20 +0000 |
| commit | 703778cb839b29bb2d80be90155667121c3f90b0 (patch) | |
| tree | ff0ef40707fb395969cbdf4ec0adc57511cd04ba | |
| parent | 18d8fe27b202ade0ad66194e84efed248b674bd7 (diff) | |
soc/amd/mendocino/acpi/pci_int_defs: remove TODO after checking
All field definitions in the IndexField object match both the info in
the PPR #57243 revision 3.02 and also match the defines in soc/amd/
mendocino/include/soc/amd_pci_int_defs.h. The IndexFieldvonly defines
the subset of the IRQ mapping registers that are used or likely needed
in the future. This is handled in the same way for the other AMD SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b0adfecc99945de69b4853f4423b4c10951d3e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72092
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/mendocino/acpi/pci_int_defs.asl | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/mendocino/acpi/pci_int_defs.asl b/src/soc/amd/mendocino/acpi/pci_int_defs.asl index fa5c88b0d6..6d194036d4 100644 --- a/src/soc/amd/mendocino/acpi/pci_int_defs.asl +++ b/src/soc/amd/mendocino/acpi/pci_int_defs.asl @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Check if this is still correct */ - /* PCI IRQ mapping registers, C00h-C01h. */ OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) Field(PRQM, ByteAcc, NoLock, Preserve) { |